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| author | Florian Fainelli <f.fainelli@gmail.com> | 2020-07-07 07:56:00 +0300 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2020-07-07 07:56:00 +0300 |
| commit | aee13efe44c10b747e6b59659a242d8f7d266e92 (patch) | |
| tree | 10ba090495c33a83432fbe48e2bf23a9a326fbf2 | |
| parent | c4f294fd2fd23376cbafd277c672053e38e76e5d (diff) | |
| parent | 25c6f3960764b266a609281341f889a06d045039 (diff) | |
| download | linux-aee13efe44c10b747e6b59659a242d8f7d266e92.tar.xz | |
Merge tag 'tags/bcm2835-dt-next-2020-07-06' into devicetree/next
Maxime Ripard introduces two new clock providers into RPi4's device tree:
- The first one based on the enhancements made to clk-raspberrypi, which
is now registered trough DT and provides control over the whole range
of firmware based clocks.
- The second one based on the new clk-bcm2711-dvp driver, which gates
the clocks and reset signals that feed into RPi4's HDMI0/1 blocks.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| -rw-r--r-- | arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/bcm2711.dtsi | 15 |
2 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index c7f1d97e69bb..222d7825e1ab 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -69,6 +69,11 @@ }; &firmware { + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; + expgpio: gpio { compatible = "raspberrypi,firmware-gpio"; gpio-controller; diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index a91cf68e3c4c..00bcaed1be32 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -12,6 +12,13 @@ interrupt-parent = <&gicv2>; + clk_108MHz: clk-108M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <108000000>; + clock-output-names = "108MHz-clock"; + }; + soc { /* * Defined ranges: @@ -244,6 +251,14 @@ hvs@7e400000 { interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; }; + + dvp: clock@7ef00000 { + compatible = "brcm,brcm2711-dvp"; + reg = <0x7ef00000 0x10>; + clocks = <&clk_108MHz>; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; /* |
