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| author | Sowon Na <sowon.na@samsung.com> | 2026-04-17 15:14:52 +0300 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2026-05-14 19:36:34 +0300 |
| commit | ae326b14b2a5a5e426bea0210b984ee8dc5ed0bb (patch) | |
| tree | e6bab504f214f27fc5b3bff5d1a39e53ea26021f | |
| parent | 14b0c168c7038f1d9e50f27e47d8e285f52cd2a3 (diff) | |
| download | linux-ae326b14b2a5a5e426bea0210b984ee8dc5ed0bb.tar.xz | |
arm64: dts: exynosautov920: enable support for ufs controller
Add ufs node for ExynosAutov920 SoC. Also enable ufs_phy and
ufs controller nodes.
Signed-off-by: Sowon Na <sowon.na@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://patch.msgid.link/20260417121452.827054-5-alim.akhtar@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts | 8 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 21 |
2 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts index a397f068ed53..5873720c213e 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts @@ -83,6 +83,14 @@ status = "okay"; }; +&ufs_0 { + status = "okay"; +}; + +&ufs_0_phy { + status = "okay"; +}; + &xtcxo { clock-frequency = <38400000>; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 0eb853770732..f1f5efcdb91e 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1444,6 +1444,27 @@ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; }; + ufs_0: ufs@16e00000 { + compatible = "samsung,exynosautov920-ufs"; + reg = <0x16e00000 0x100>, + <0x16e01100 0x400>, + <0x16e80000 0x8000>, + <0x16d08000 0x800>; + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_hsi2 CLK_MOUT_HSI2_UFS_EMBD_USER>, + <&cmu_hsi2 CLK_MOUT_HSI2_NOC_UFS_USER>; + clock-names = "core_clk", "sclk_unipro_main"; + freq-table-hz = <0 0>, <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + phys = <&ufs_0_phy>; + phy-names = "ufs-phy"; + samsung,sysreg = <&syscon_hsi2 0x710>; + dma-coherent; + status = "disabled"; + }; + ufs_0_phy: phy@16e04000 { compatible = "samsung,exynosautov920-ufs-phy"; reg = <0x16e04000 0x4000>; |