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authorCosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>2025-12-01 16:42:23 +0300
committerMark Brown <broonie@kernel.org>2025-12-14 13:38:33 +0300
commita886baaaa6e12a9b7d5a9687d11d3b895f1b87c9 (patch)
treec9db53918675ef59bc7fb24c133dd73cda9f1725
parent6f9026b5a18acdf190d1622831b100aacfca0eb3 (diff)
downloadlinux-a886baaaa6e12a9b7d5a9687d11d3b895f1b87c9.tar.xz
spi: rzv2h-rspi: set TX FIFO threshold to 0
In PIO mode we send data word-by-word, and wait for the received data to be available after each sent word, making no use of the TX interrupt. In DMA mode, we need to set the RX and TX FIFO thresholds to 0, as described in the User Manual. In preparation for implementing DMA support, set TX FIFO threshold to 0, as RX FIFO threshold is already 0. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Link: https://patch.msgid.link/20251201134229.600817-8-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--drivers/spi/spi-rzv2h-rspi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-rzv2h-rspi.c b/drivers/spi/spi-rzv2h-rspi.c
index f0bbbd21c763..83bb0b7400b2 100644
--- a/drivers/spi/spi-rzv2h-rspi.c
+++ b/drivers/spi/spi-rzv2h-rspi.c
@@ -501,7 +501,7 @@ static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr,
writeb(0, rspi->base + RSPI_SSLP);
/* Setup FIFO thresholds */
- conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, rspi->info->fifo_size - 1);
+ conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, 0);
conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0);
writew(conf16, rspi->base + RSPI_SPDCR2);