diff options
| author | Sandie Cao <sandie.cao@deepcomputing.io> | 2025-03-24 05:09:58 +0300 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2025-05-15 23:05:45 +0300 |
| commit | a2e7f6c48740bac078863227ce91a40f65d428c9 (patch) | |
| tree | 2ecb0d44a30d15c731c084227a00d1db76f26868 | |
| parent | 0af2f6be1b4281385b618cb86ad946eded089ac8 (diff) | |
| download | linux-a2e7f6c48740bac078863227ce91a40f65d428c9.tar.xz | |
riscv: dts: starfive: fml13v01: enable USB 3.0 port
Add usb_cdns3 and usb0_pins configuration to support super speed USB
device on the FML13V01 board.
Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io>
Tested-by: Maud Spierings <maud_spierings@hotmail.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts index 8d9ce8b69a71..f2857d021d68 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts @@ -43,9 +43,28 @@ slew-rate = <0>; }; }; + + usb0_pins: usb0-0 { + vbus-pins { + pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, + GPOEN_ENABLE, + GPI_NONE)>; + bias-disable; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; }; &usb0 { dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; status = "okay"; }; + +&usb_cdns3 { + phys = <&usbphy0>, <&pciephy0>; + phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; +}; |