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authorRobert Marko <robimarko@gmail.com>2023-10-04 22:12:30 +0300
committerBjorn Andersson <andersson@kernel.org>2023-10-16 21:48:24 +0300
commita1f42e08f0f04b72a6597f080db4bfbb3737910c (patch)
tree8e3207a80c9487956183af72cae98553484e61b3
parent27c2ca90e2f34cd3c4849af996e1a96a69e700d3 (diff)
downloadlinux-a1f42e08f0f04b72a6597f080db4bfbb3737910c.tar.xz
arm64: dts: qcom: ipq5018: add QUP1 SPI controller
Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20231004191303.331055-1-robimarko@gmail.com [bjorn: Padded address to 8 digits, fixed node sort order] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--arch/arm64/boot/dts/qcom/ipq5018.dtsi24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 340b90cc17db..0b739077ed70 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -159,6 +159,16 @@
status = "disabled";
};
+ blsp_dma: dma-controller@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07884000 0x1d000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
@@ -169,6 +179,20 @@
status = "disabled";
};
+ blsp1_spi1: spi@78b5000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x078b5000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
usb: usb@8af8800 {
compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x400>;