summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGustavo Sousa <gustavo.sousa@intel.com>2026-02-06 21:35:59 +0300
committerGustavo Sousa <gustavo.sousa@intel.com>2026-02-10 16:08:54 +0300
commita08104551d08cf5c1542ba552bd7d1cf9d4ecd23 (patch)
tree99a4544e811ac1ffc3cff1a1a118d30c746ab6c4
parent835cd6cbb0d0e44c3fc4efc1ba6c79ffb2e2f751 (diff)
downloadlinux-a08104551d08cf5c1542ba552bd7d1cf9d4ecd23.tar.xz
drm/xe/pat: Differentiate between primary and media for PTA
Differently from currently supported platforms, in upcoming changes we will need to have different PAT entries for PTA based on the GT type. As such, let's prepare the code to support that by having two separate PTA-specific members in the pat struct, one for each type of GT. While at it, also fix the kerneldoc for pat_ats. Co-developed-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260206-nvl-p-upstreaming-v3-3-636e1ad32688@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
-rw-r--r--drivers/gpu/drm/xe/xe_device_types.h8
-rw-r--r--drivers/gpu/drm/xe/xe_pat.c27
2 files changed, 23 insertions, 12 deletions
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 14bf2c027f89..059f026e80d5 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -400,10 +400,12 @@ struct xe_device {
const struct xe_pat_table_entry *table;
/** @pat.n_entries: Number of PAT entries */
int n_entries;
- /** @pat.ats_entry: PAT entry for PCIe ATS responses */
+ /** @pat.pat_ats: PAT entry for PCIe ATS responses */
const struct xe_pat_table_entry *pat_ats;
- /** @pat.pta_entry: PAT entry for page table accesses */
- const struct xe_pat_table_entry *pat_pta;
+ /** @pat.pat_primary_pta: primary GT PAT entry for page table accesses */
+ const struct xe_pat_table_entry *pat_primary_pta;
+ /** @pat.pat_media_pta: media GT PAT entry for page table accesses */
+ const struct xe_pat_table_entry *pat_media_pta;
u32 idx[__XE_CACHE_LEVEL_COUNT];
} pat;
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 2cd3fd1c3953..5ba650948a4a 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -285,8 +285,10 @@ static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[
if (xe->pat.pat_ats)
xe_mmio_write32(&gt->mmio, XE_REG(_PAT_ATS), xe->pat.pat_ats->value);
- if (xe->pat.pat_pta)
- xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe->pat.pat_pta->value);
+ if (xe->pat.pat_primary_pta && xe_gt_is_main_type(gt))
+ xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe->pat.pat_primary_pta->value);
+ if (xe->pat.pat_media_pta && xe_gt_is_media_type(gt))
+ xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe->pat.pat_media_pta->value);
}
static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[],
@@ -302,8 +304,10 @@ static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry ta
if (xe->pat.pat_ats)
xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value);
- if (xe->pat.pat_pta)
- xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_pta->value);
+ if (xe->pat.pat_primary_pta && xe_gt_is_main_type(gt))
+ xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_primary_pta->value);
+ if (xe->pat.pat_media_pta && xe_gt_is_media_type(gt))
+ xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_media_pta->value);
}
static int xelp_dump(struct xe_gt *gt, struct drm_printer *p)
@@ -498,7 +502,8 @@ void xe_pat_init_early(struct xe_device *xe)
xe->pat.ops = &xe3p_xpc_pat_ops;
xe->pat.table = xe3p_xpc_pat_table;
xe->pat.pat_ats = &xe3p_xpc_pat_ats;
- xe->pat.pat_pta = &xe3p_xpc_pat_pta;
+ xe->pat.pat_primary_pta = &xe3p_xpc_pat_pta;
+ xe->pat.pat_media_pta = &xe3p_xpc_pat_pta;
xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
xe->pat.idx[XE_CACHE_NONE] = 3;
xe->pat.idx[XE_CACHE_WT] = 3; /* N/A (no display); use UC */
@@ -512,8 +517,10 @@ void xe_pat_init_early(struct xe_device *xe)
xe->pat.table = xe2_pat_table;
}
xe->pat.pat_ats = &xe2_pat_ats;
- if (IS_DGFX(xe))
- xe->pat.pat_pta = &xe2_pat_pta;
+ if (IS_DGFX(xe)) {
+ xe->pat.pat_primary_pta = &xe2_pat_pta;
+ xe->pat.pat_media_pta = &xe2_pat_pta;
+ }
/* Wa_16023588340. XXX: Should use XE_WA */
if (GRAPHICS_VERx100(xe) == 2001)
@@ -617,6 +624,8 @@ int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p)
int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
{
struct xe_device *xe = gt_to_xe(gt);
+ const struct xe_pat_table_entry *pta_entry = xe_gt_is_main_type(gt) ?
+ xe->pat.pat_primary_pta : xe->pat.pat_media_pta;
char label[PAT_LABEL_LEN];
if (!xe->pat.table || !xe->pat.n_entries)
@@ -640,8 +649,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
}
}
- if (xe->pat.pat_pta) {
- u32 pat = xe->pat.pat_pta->value;
+ if (pta_entry) {
+ u32 pat = pta_entry->value;
drm_printf(p, "Page Table Access:\n");
xe->pat.ops->entry_dump(p, "PTA_MODE", pat, false);