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| author | Sibi Sankar <quic_sibis@quicinc.com> | 2024-06-12 15:40:54 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-10-16 23:26:31 +0300 |
| commit | 9ed1a2b8784262e85ec300792a1a37ebd8473be2 (patch) | |
| tree | 150f188c22dd52d4108a2d6f1daca5a584b89add | |
| parent | 87c1870b5aea744d73f0e4442a285056c64d1239 (diff) | |
| download | linux-9ed1a2b8784262e85ec300792a1a37ebd8473be2.tar.xz | |
arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region
Resize the GICR register region as it currently seeps into the CPU Control
Processor mailbox RX region.
Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Link: https://lore.kernel.org/r/20240612124056.39230-4-quic_sibis@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index f3fb527c0b08..a85a7bdfbf52 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5754,7 +5754,7 @@ intc: interrupt-controller@17000000 { compatible = "arm,gic-v3"; reg = <0 0x17000000 0 0x10000>, /* GICD */ - <0 0x17080000 0 0x480000>; /* GICR * 12 */ + <0 0x17080000 0 0x300000>; /* GICR * 12 */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |