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authorIvaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>2024-10-23 12:17:32 +0300
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>2024-10-26 15:08:04 +0300
commit9ad6c3bd1bcbb73e2a5723e13b9d06e2296b07e4 (patch)
treeac812e0069cf6cc0e4ebf09de42fdfc7eb37917e
parentfa986d1073805154888a788eda38d46a796346e8 (diff)
downloadlinux-9ad6c3bd1bcbb73e2a5723e13b9d06e2296b07e4.tar.xz
arm64: dts: exynos8895: Add Multi Core Timer (MCT) node
MCT has one global timer and 8 CPU local timers. The global timer can generate 4 interrupts, and each local timer can generate an interrupt making 12 interrupts in total. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241023091734.538682-4-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-rw-r--r--arch/arm64/boot/dts/exynos/exynos8895.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi
index 54037b0dc630..e6c8a49668e2 100644
--- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi
@@ -169,6 +169,26 @@
clock-names = "oscclk", "bus";
};
+ timer@10040000 {
+ compatible = "samsung,exynos8895-mct",
+ "samsung,exynos4210-mct";
+ reg = <0x10040000 0x800>;
+ clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>;
+ clock-names = "fin_pll", "mct";
+ interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
gic: interrupt-controller@10201000 {
compatible = "arm,gic-400";
reg = <0x10201000 0x1000>,