diff options
| author | Eric Yang <Eric.Yang2@amd.com> | 2017-06-27 19:09:01 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-27 01:08:39 +0300 |
| commit | 966443b592753f6498f896b4afc7c2df1352af72 (patch) | |
| tree | 0fb2e8e7c380408027f958e9db3c8f51f15d0ff1 | |
| parent | f42485bb6d1171272d5ecb5b6213505b14294472 (diff) | |
| download | linux-966443b592753f6498f896b4afc7c2df1352af72.tar.xz | |
drm/amd/display: block modes that require read bw greater than 30%
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 18 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 1 |
2 files changed, 18 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 93384a3f3525..24f8c4496a61 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -95,6 +95,9 @@ const struct dcn_soc_bounding_box dcn10_soc_defaults = { .vmm_page_size = 4096, /*bytes*/ .return_bus_width = 64, /*bytes*/ .max_request_size = 256, /*bytes*/ + + /* Depends on user class (client vs embedded, workstation, etc) */ + .percent_disp_bw_limit = 0.3f /*%*/ }; const struct dcn_ip_params dcn10_ip_defaults = { @@ -695,6 +698,8 @@ bool dcn_validate_bandwidth( struct dcn_bw_internal_vars *v = &context->dcn_bw_vars; int i, input_idx; int vesa_sync_start, asic_blank_end, asic_blank_start; + bool bw_limit_pass; + float bw_limit; if (dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public))) dcn_bw_sync_calcs_and_dml(DC_TO_CORE(&dc->public)); @@ -1072,8 +1077,19 @@ bool dcn_validate_bandwidth( dc_core->dml.soc.sr_exit_time_us = dc_core->dcn_soc.sr_exit_time; } + /* + * BW limit is set to prevent display from impacting other system functions + */ + + bw_limit = dc->dcn_soc.percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9; + bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit; + kernel_fpu_end(); - return v->voltage_level != 5; + + if (bw_limit_pass && v->voltage_level != 5) + return true; + else + return false; } unsigned int dcn_find_normalized_clock_vdd_Level( diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h index 499bc1127696..b6cc07450f1f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h @@ -572,6 +572,7 @@ struct dcn_soc_bounding_box { int vmm_page_size; /*bytes*/ float dram_clock_change_latency; /*us*/ int return_bus_width; /*bytes*/ + float percent_disp_bw_limit; /*%*/ }; extern const struct dcn_soc_bounding_box dcn10_soc_defaults; |