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author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2025-01-14 14:54:19 +0300 |
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committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2025-01-14 15:29:27 +0300 |
commit | 961d234779867695a7724fd4fb0a5a1bd3d4ccab (patch) | |
tree | a5e65e3603e253b7ea0b7f3f331d384ec60cb156 | |
parent | 50867db066cda563902c9c203dc8f9b5a11c1e78 (diff) | |
download | linux-961d234779867695a7724fd4fb0a5a1bd3d4ccab.tar.xz |
ARM: 9432/2: add CLIDR accessor functions
Add functions to read the CLIDR, Cache Level ID Register.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
-rw-r--r-- | arch/arm/include/asm/cachetype.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h index b9dbe1d4c8fe..b01c59076b84 100644 --- a/arch/arm/include/asm/cachetype.h +++ b/arch/arm/include/asm/cachetype.h @@ -83,6 +83,14 @@ static inline unsigned int read_ccsidr(void) asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); return val; } + +static inline unsigned int read_clidr(void) +{ + unsigned int val; + + asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (val)); + return val; +} #else /* CONFIG_CPU_V7M */ #include <linux/io.h> #include "asm/v7m.h" @@ -96,6 +104,11 @@ static inline unsigned int read_ccsidr(void) { return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR); } + +static inline unsigned int read_clidr(void) +{ + return readl(BASEADDR_V7M_SCB + V7M_SCB_CLIDR); +} #endif #endif |