drm/ast: Replace references to struct drm_format_info.cpp

Replace all uses of struct drm_format_info.cpp with the corresponding
4CC constant. Color-mode selection uses switch statements that branch
by cpp in several places. While at it, also name the involved variables
according to register names and replace magic values with constants.

Replace the use of *ModeIndex constants in ast_set_vbios_color_reg()
with correct register constants. The former are array indices and do
not belong into registers.

In ast_set_color_reg(), vgacra0 is independent from the color format,
so move it out from the switch statements.

There is also a flag for gamma correction in vgacra8, which currently
ast_set_color_reg() handles as part of the primary plane. The gamma LUT
and its programming is located in the CRTC. A future update should
consolidate gamma correction in the primary plane and implement the
functionality with DRM's colorop helpers.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patch.msgid.link/20260414070522.33943-4-tzimmermann@suse.de

2 files changed, 77 insertions, 43 deletions

diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index 49585fd16267..340ea680df47 100644
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -146,29 +146,31 @@ static void ast_set_vbios_color_reg(struct ast_device *ast,
 				    const struct drm_format_info *format,
 				    const struct ast_vbios_enhtable *vmode)
 {
-	u32 color_index;
+	u8 vgacr8c = 0x00;
+	u8 vgacr92 = 0x00;
 
-	switch (format->cpp[0]) {
-	case 1:
-		color_index = VGAModeIndex - 1;
+	switch (format->format) {
+	case DRM_FORMAT_C8:
+		vgacr8c |= AST_IO_VGACR8C_CUR_MODE_VGA;
+		vgacr92 = 8;
 		break;
-	case 2:
-		color_index = HiCModeIndex;
+	case DRM_FORMAT_RGB565:
+		vgacr8c |= AST_IO_VGACR8C_CUR_MODE_16_BPP;
+		vgacr92 = 16;
 		break;
-	case 4:
-		color_index = TrueCModeIndex;
+	case DRM_FORMAT_XRGB8888:
+		vgacr8c |= AST_IO_VGACR8C_CUR_MODE_32_BPP;
+		vgacr92 = 32;
 		break;
-	default:
-		return;
 	}
 
-	ast_set_index_reg(ast, AST_IO_VGACRI, 0x8c, (u8)((color_index & 0x0f) << 4));
+	ast_set_index_reg(ast, AST_IO_VGACRI, 0x8c, vgacr8c);
 
 	ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00);
 
 	if (vmode->flags & NewModeInfo) {
 		ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, AST_IO_VGACR91_PASSWORD);
-		ast_set_index_reg(ast, AST_IO_VGACRI, 0x92, format->cpp[0] * 8);
+		ast_set_index_reg(ast, AST_IO_VGACRI, 0x92, vgacr92);
 	}
 }
 
@@ -380,30 +382,33 @@ static void ast_set_dclk_reg(struct ast_device *ast,
 static void ast_set_color_reg(struct ast_device *ast,
 			      const struct drm_format_info *format)
 {
-	u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
+	u8 vgacra0 = 0x00;
+	u8 vgacra3 = 0x00;
+	u8 vgacra8 = 0x00;
 
-	switch (format->cpp[0] * 8) {
-	case 8:
-		jregA0 = 0x70;
-		jregA3 = 0x01;
-		jregA8 = 0x00;
+	vgacra0 |= AST_IO_VGACRA0_MEMORY_CHAIN4_MODE |
+		   AST_IO_VGACRA0_LINEAR_EXT_ACCESS |
+		   AST_IO_VGACRA0_SEGMENTED_EXT_ACCESS;
+
+	switch (format->format) {
+	case DRM_FORMAT_C8:
+		vgacra3 |= AST_IO_VGACRA3_256_COLORS;
+		vgacra8 &= ~AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED;
 		break;
-	case 15:
-	case 16:
-		jregA0 = 0x70;
-		jregA3 = 0x04;
-		jregA8 = 0x02;
+	case DRM_FORMAT_XRGB1555:
+	case DRM_FORMAT_RGB565:
+		vgacra3 |= AST_IO_VGACRA3_16_BPP;
+		vgacra8 |= AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED;
 		break;
-	case 32:
-		jregA0 = 0x70;
-		jregA3 = 0x08;
-		jregA8 = 0x02;
+	case DRM_FORMAT_XRGB8888:
+		vgacra3 |= AST_IO_VGACRA3_32_BPP;
+		vgacra8 |= AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED;
 		break;
 	}
 
-	ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa0, 0x8f, jregA0);
-	ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xf0, jregA3);
-	ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa8, 0xfd, jregA8);
+	ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa0, 0x8f, vgacra0);
+	ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xf0, vgacra3);
+	ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa8, 0xfd, vgacra8);
 }
 
 static void ast_set_crtthd_reg(struct ast_device *ast)
diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h
index 99d0a8322f89..9267b70a3ec8 100644
--- a/drivers/gpu/drm/ast/ast_reg.h
+++ b/drivers/gpu/drm/ast/ast_reg.h
@@ -28,19 +28,48 @@
 #define AST_IO_VGAPDR		        (0x49)
 #define AST_IO_VGAGRI			(0x4E)
 
-#define AST_IO_VGACRI			(0x54)
-#define AST_IO_VGACR17_SYNC_ENABLE	BIT(7) /* called "Hardware reset" in docs */
-#define AST_IO_VGACR80_PASSWORD		(0xa8)
-#define AST_IO_VGACR91_PASSWORD		(0xa8)
-#define AST_IO_VGACR99_VGAMEM_RSRV_MASK	GENMASK(1, 0)
-#define AST_IO_VGACRA1_VGAIO_DISABLED	BIT(1)
-#define AST_IO_VGACRA1_MMIO_ENABLED	BIT(2)
-#define AST_IO_VGACRA3_DVO_ENABLED	BIT(7)
-#define AST_IO_VGACRAA_VGAMEM_SIZE_MASK	GENMASK(1, 0)
-#define AST_IO_VGACRB6_HSYNC_OFF	BIT(0)
-#define AST_IO_VGACRB6_VSYNC_OFF	BIT(1)
-#define AST_IO_VGACRCB_HWC_16BPP	BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
-#define AST_IO_VGACRCB_HWC_ENABLED	BIT(1)
+#define AST_IO_VGACRI				(0x54)
+#define AST_IO_VGACR17_SYNC_ENABLE		BIT(7) /* called "Hardware reset" in docs */
+#define AST_IO_VGACR80_PASSWORD			(0xa8)
+
+#define AST_IO_VGACR8C_NEW_MODE_MASK		GENMASK(3, 0)
+#define AST_IO_VGACR8C_NEW_MODE_EGA		(0x00)
+#define AST_IO_VGACR8C_NEW_MODE_VGA		(0x01)
+#define AST_IO_VGACR8C_NEW_MODE_15_BPP		(0x02)
+#define AST_IO_VGACR8C_NEW_MODE_16_BPP		(0x03)
+#define AST_IO_VGACR8C_NEW_MODE_32_BPP		(0x04)
+#define AST_IO_VGACR8C_NEW_MODE_CGA		(0x0f)
+#define AST_IO_VGACR8C_NEW_MODE_TEXT		(0x0e)
+#define AST_IO_VGACR8C_CUR_MODE_MASK		GENMASK(7, 4)
+#define AST_IO_VGACR8C_CUR_MODE_EGA		(0x00)
+#define AST_IO_VGACR8C_CUR_MODE_VGA		(0x10)
+#define AST_IO_VGACR8C_CUR_MODE_15_BPP		(0x20)
+#define AST_IO_VGACR8C_CUR_MODE_16_BPP		(0x30)
+#define AST_IO_VGACR8C_CUR_MODE_32_BPP		(0x40)
+#define AST_IO_VGACR8C_CUR_MODE_CGA		(0xf0)
+#define AST_IO_VGACR8C_CUR_MODE_TEXT		(0xe0)
+
+#define AST_IO_VGACR91_PASSWORD			(0xa8)
+#define AST_IO_VGACR99_VGAMEM_RSRV_MASK		GENMASK(1, 0)
+
+#define AST_IO_VGACRA0_MEMORY_CHAIN4_MODE	BIT(6)
+#define AST_IO_VGACRA0_LINEAR_EXT_ACCESS	BIT(5)
+#define AST_IO_VGACRA0_SEGMENTED_EXT_ACCESS	BIT(4)
+
+#define AST_IO_VGACRA1_VGAIO_DISABLED		BIT(1)
+#define AST_IO_VGACRA1_MMIO_ENABLED		BIT(2)
+
+#define AST_IO_VGACRA3_DVO_ENABLED		BIT(7)
+#define AST_IO_VGACRA3_32_BPP			BIT(3)
+#define AST_IO_VGACRA3_16_BPP			BIT(2)
+#define AST_IO_VGACRA3_256_COLORS		BIT(0)
+
+#define AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED	BIT(1)
+#define AST_IO_VGACRAA_VGAMEM_SIZE_MASK		GENMASK(1, 0)
+#define AST_IO_VGACRB6_HSYNC_OFF		BIT(0)
+#define AST_IO_VGACRB6_VSYNC_OFF		BIT(1)
+#define AST_IO_VGACRCB_HWC_16BPP		BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
+#define AST_IO_VGACRCB_HWC_ENABLED		BIT(1)
 
 /* mirrors SCU100[7:0] */
 #define AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK	GENMASK(7, 6)