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authorAxe Yang <axe.yang@mediatek.com>2025-04-11 08:40:25 +0300
committerUlf Hansson <ulf.hansson@linaro.org>2025-05-14 17:59:18 +0300
commit920e6bfa6a11baf4fae0e5ce9e3b70f59ae0d47a (patch)
tree478fd49e9603fbc8bd92d30e02bc7bda47450bad
parent1c7387579d743c02a3da7aefff1689a5a55c9b84 (diff)
downloadlinux-920e6bfa6a11baf4fae0e5ce9e3b70f59ae0d47a.tar.xz
mmc: mtk-sd: Add condition to enable 'single' burst type
This change add a condition for 'single' burst type selection. Read AXI_LEN field from EMMC50_CFG2(AHB2AXI wrapper) register, if the value is not 0, it means the HWIP is using AXI as AMBA bus, which do not support 'single' burst type. Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Axe Yang <axe.yang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250411054134.31822-1-axe.yang@mediatek.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-rw-r--r--drivers/mmc/host/mtk-sd.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index a9bd0bc4d4eb..31eb90536bce 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -84,6 +84,7 @@
#define EMMC51_CFG0 0x204
#define EMMC50_CFG0 0x208
#define EMMC50_CFG1 0x20c
+#define EMMC50_CFG2 0x21c
#define EMMC50_CFG3 0x220
#define SDC_FIFO_CFG 0x228
#define CQHCI_SETTING 0x7fc
@@ -306,7 +307,10 @@
/* EMMC50_CFG1 mask */
#define EMMC50_CFG1_DS_CFG BIT(28) /* RW */
-#define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
+/* EMMC50_CFG2 mask */
+#define EMMC50_CFG2_AXI_SET_LEN GENMASK(27, 24) /* RW */
+
+#define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
#define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */
#define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */
@@ -1917,9 +1921,13 @@ static void msdc_init_hw(struct msdc_host *host)
pb1_val |= FIELD_PREP(MSDC_PATCH_BIT1_CMDTA, 1);
pb1_val |= MSDC_PB1_DDR_CMD_FIX_SEL;
- /* Set single burst mode, auto sync state clear, block gap stop clk */
- pb1_val |= MSDC_PB1_SINGLE_BURST | MSDC_PB1_RSVD20 |
- MSDC_PB1_AUTO_SYNCST_CLR | MSDC_PB1_MARK_POP_WATER;
+ /* Support 'single' burst type only when AXI_LEN is 0 */
+ sdr_get_field(host->base + EMMC50_CFG2, EMMC50_CFG2_AXI_SET_LEN, &val);
+ if (!val)
+ pb1_val |= MSDC_PB1_SINGLE_BURST;
+
+ /* Set auto sync state clear, block gap stop clk */
+ pb1_val |= MSDC_PB1_RSVD20 | MSDC_PB1_AUTO_SYNCST_CLR | MSDC_PB1_MARK_POP_WATER;
/* Set low power DCM, use HCLK for GDMA, use MSDC CLK for everything else */
pb1_val |= MSDC_PB1_LP_DCM_EN | MSDC_PB1_RSVD3 |