diff options
| author | Evan Quan <evan.quan@amd.com> | 2020-09-25 09:34:40 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-27 19:00:09 +0300 |
| commit | 8f97e221d64d76b8c80b5fa6b41a9a77b8ab1c9f (patch) | |
| tree | 51220511905650b19ad2753827b64405e8a64312 | |
| parent | ba4601feba44b93e749abe0ddccda8c8df31be12 (diff) | |
| download | linux-8f97e221d64d76b8c80b5fa6b41a9a77b8ab1c9f.tar.xz | |
drm/amd/pm: correct pcie spc cap setup
Correct Polaris10 pcie spc cap setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c index 7eca860236db..59c199cd7aeb 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c @@ -2865,6 +2865,8 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) data->pcie_gen_cap = adev->pm.pcie_gen_mask; if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) data->pcie_spc_cap = 20; + else + data->pcie_spc_cap = 16; data->pcie_lane_cap = adev->pm.pcie_mlw_mask; hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ |