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authorAbel Vesa <abel.vesa@linaro.org>2024-01-29 15:45:37 +0300
committerBjorn Andersson <andersson@kernel.org>2024-02-06 20:14:29 +0300
commit8b6e2bf94b278c69746358425daae2a75041f7dc (patch)
tree3b4dd0f857e2a0c72a5e944e6af7a1567078b898
parent5f2a9cd4b1042ade3824cfe324aa02a3c17430a8 (diff)
downloadlinux-8b6e2bf94b278c69746358425daae2a75041f7dc.tar.xz
arm64: dts: qcom: x1e80100: Add TCSR node
Add the TCSR clock controller and register space node. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-5-2c0e691cfa3b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--arch/arm64/boot/dts/qcom/x1e80100.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 22ba653714f4..54827eaca746 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -2614,6 +2614,14 @@
#hwlock-cells = <1>;
};
+ tcsr: clock-controller@1fc0000 {
+ compatible = "qcom,x1e80100-tcsr", "syscon";
+ reg = <0 0x01fc0000 0 0x30000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
gem_noc: interconnect@26400000 {
compatible = "qcom,x1e80100-gem-noc";
reg = <0 0x26400000 0 0x311200>;