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authorMarc Zyngier <maz@kernel.org>2024-10-23 17:53:24 +0300
committerOliver Upton <oliver.upton@linux.dev>2024-10-31 05:42:31 +0300
commit874ae1d48e607d41ae08fa72a9ed76cb62651085 (patch)
treefeedf925fed7938fd19ff5568b27abd63ddb310e
parentb3ad940a088761fd183dccd65c6ee20b360e8c4b (diff)
downloadlinux-874ae1d48e607d41ae08fa72a9ed76cb62651085.tar.xz
KVM: arm64: Handle PIR{,E0}_EL2 traps
Add the FEAT_S1PIE EL2 registers the sysreg descriptor array so that they can be handled as a trap. Access to these registers is conditional based on ID_AA64MMFR3_EL1.S1PIE being advertised. Similarly to other other changes, PIRE0_EL2 is guaranteed to trap thanks to the D22677 update to the architecture. Reviewed-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20241023145345.1613824-17-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
-rw-r--r--arch/arm64/kvm/sys_regs.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 9cbcd69d45fc..2d30266a4c65 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -369,6 +369,18 @@ static bool access_rw(struct kvm_vcpu *vcpu,
return true;
}
+static bool check_s1pie_access_rw(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) {
+ kvm_inject_undefined(vcpu);
+ return false;
+ }
+
+ return access_rw(vcpu, p, r);
+}
+
/*
* See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
*/
@@ -2909,6 +2921,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
+ EL2_REG(PIRE0_EL2, check_s1pie_access_rw, reset_val, 0),
+ EL2_REG(PIR_EL2, check_s1pie_access_rw, reset_val, 0),
EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
EL2_REG(VBAR_EL2, access_rw, reset_val, 0),