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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-05-13 02:36:49 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:33:50 +0300 |
| commit | 85635f5d47d7304a44bc45b419f8f31423712ef8 (patch) | |
| tree | e7c35c12a0a8dbb5e450db7aed41c6e0bd20ec08 | |
| parent | 500f90620cce13e8fd9e7dfc19701d753c4b3625 (diff) | |
| download | linux-85635f5d47d7304a44bc45b419f8f31423712ef8.tar.xz | |
drm/xe: Load HuC on Alderlake P
Alderlake P uses TGL HuC and it was not added together with ADL-S,
because it was failing for unrelated reasons. Now that those are fixed,
allow it to load HuC.
# cat /sys/kernel/debug/dri/0/gt0/uc/huc_info
HuC firmware: i915/tgl_huc.bin
status: RUNNING
version: wanted 0.0, found 7.9
uCode: 589504 bytes
RSA: 256 bytes
HuC status: 0x00090001
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://lore.kernel.org/r/20230512233649.3218736-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| -rw-r--r-- | drivers/gpu/drm/xe/xe_uc_fw.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c index 609ca3f2ffa4..5703213bdf1b 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw.c +++ b/drivers/gpu/drm/xe/xe_uc_fw.c @@ -111,6 +111,7 @@ struct fw_blobs_by_type { fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 5)) #define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver) \ + fw_def(ALDERLAKE_P, no_ver(i915, huc, tgl)) \ fw_def(ALDERLAKE_S, no_ver(i915, huc, tgl)) \ fw_def(DG1, no_ver(i915, huc, dg1)) \ fw_def(ROCKETLAKE, no_ver(i915, huc, tgl)) \ |