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| author | Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> | 2026-01-20 20:22:50 +0300 |
|---|---|---|
| committer | Linus Walleij <linusw@kernel.org> | 2026-01-21 15:11:56 +0300 |
| commit | 84a3bc337378385ed9c9cef06910587de7accf0b (patch) | |
| tree | b4b207bc652e6a9f1552cad8ad33e1f650649dad | |
| parent | 450e2487d5a28260f70ad7fbf3060e7f8304203d (diff) | |
| download | linux-84a3bc337378385ed9c9cef06910587de7accf0b.tar.xz | |
dt-bindings: pinctrl: qcom,glymur-tlmm: Document Mahua TLMM block
Document the pinctrl compatible for the Mahua SoC, a 12-core variant
of Glymur. The PDC wake IRQ map differs since PDC handles the interrupt
for GPIO 155 instead of GPIO 143 as seen on Glymur.
Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml index d2b0cfeffb50..2836a1a10579 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml @@ -10,14 +10,16 @@ maintainers: - Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> description: - Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC. + Top Level Mode Multiplexer pin controller in Qualcomm Glymur and Mahua SoC. allOf: - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# properties: compatible: - const: qcom,glymur-tlmm + enum: + - qcom,glymur-tlmm + - qcom,mahua-tlmm reg: maxItems: 1 |