diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-12-08 21:26:27 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-01-23 06:20:27 +0300 |
| commit | 7e47a14b02fe288029448f8ba80852fe2b0b2d53 (patch) | |
| tree | e43c61fdd143221a7ff3e2d968a0869cdf0fd354 | |
| parent | 01f827140bcbde9f6b4ce68bc7657f9bb9739a69 (diff) | |
| download | linux-7e47a14b02fe288029448f8ba80852fe2b0b2d53.tar.xz | |
drm/i915/vga: Assert that VGA register accesses are going to the right GPU
We want our VGA register accesses to land on the correct GPU.
Check that the VGA routing is appropriately configured.
For the iGPU this just means the IO decode enable on the GPU, but
for dGPUs we also need the entire chain of bridges to forward the
VGA accesses.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251208182637.334-10-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_vga.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index f2f7d396c556..e51451966f72 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -58,6 +58,28 @@ static bool has_vga_pipe_sel(struct intel_display *display) return DISPLAY_VER(display) < 7; } +static bool intel_pci_has_vga_io_decode(struct pci_dev *pdev) +{ + u16 cmd = 0; + + pci_read_config_word(pdev, PCI_COMMAND, &cmd); + if ((cmd & PCI_COMMAND_IO) == 0) + return false; + + pdev = pdev->bus->self; + while (pdev) { + u16 ctl = 0; + + pci_read_config_word(pdev, PCI_BRIDGE_CONTROL, &ctl); + if ((ctl & PCI_BRIDGE_CTL_VGA) == 0) + return false; + + pdev = pdev->bus->self; + } + + return true; +} + static bool intel_pci_set_io_decode(struct pci_dev *pdev, bool enable) { u16 old = 0, cmd; @@ -169,6 +191,8 @@ void intel_vga_disable(struct intel_display *display) io_decode = intel_vga_get(display); + drm_WARN_ON(display->drm, !intel_pci_has_vga_io_decode(pdev)); + outb(0x01, VGA_SEQ_I); sr1 = inb(VGA_SEQ_D); outb(sr1 | VGA_SR01_SCREEN_OFF, VGA_SEQ_D); |