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author | Arnd Bergmann <arnd@arndb.de> | 2025-05-21 19:50:08 +0300 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2025-05-21 19:50:08 +0300 |
commit | 7e358b8cc138918381757d5e796b971bc238c6ee (patch) | |
tree | bcba6e9c7a5e256c9e04efd91a2e0f4bb9395027 | |
parent | 24822c4b476c7d7387eec21711d7908a86728d8a (diff) | |
parent | a4c95b924d513728df8631471eb3b1c300909e21 (diff) | |
download | linux-7e358b8cc138918381757d5e796b971bc238c6ee.tar.xz |
Merge tag 'thead-dt-for-v6.16' of https://github.com/pdp7/linux into soc/dt
T-HEAD Devicetrees for v6.16
There are several additions for the T-Head TH1520 SoC:
- AON (Always-On) node which serves as a power-domain controller
- Reset controller node
- VO (Video Output) clock controller node
These changes have all been tested in linux-next with the corresponding
driver patches.
Signed-off-by: Drew Fustini <drew@pdp7.com>
* tag 'thead-dt-for-v6.16' of https://github.com/pdp7/linux:
riscv: dts: thead: Add device tree VO clock controller
riscv: dts: thead: Introduce reset controller node
riscv: dts: thead: Introduce power domain nodes with aon firmware
-rw-r--r-- | arch/riscv/boot/dts/thead/th1520.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 527336417765..1db0054c4e09 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/thead,th1520-clk-ap.h> +#include <dt-bindings/power/thead,th1520-power.h> / { compatible = "thead,th1520"; @@ -229,6 +230,13 @@ snps,blen = <0 0 64 32 0 0 0>; }; + aon: aon { + compatible = "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + #power-domain-cells = <1>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -489,6 +497,19 @@ #clock-cells = <1>; }; + rst: reset-controller@ffef528000 { + compatible = "thead,th1520-reset"; + reg = <0xff 0xef528000 0x0 0x4f>; + #reset-cells = <1>; + }; + + clk_vo: clock-controller@ffef528050 { + compatible = "thead,th1520-clk-vo"; + reg = <0xff 0xef528050 0x0 0xfb0>; + clocks = <&clk CLK_VIDEO_PLL>; + #clock-cells = <1>; + }; + dmac0: dma-controller@ffefc00000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xefc00000 0x0 0x1000>; |