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authorMihai Sain <mihai.sain@microchip.com>2026-03-24 10:09:27 +0300
committerClaudiu Beznea <claudiu.beznea@tuxon.dev>2026-03-24 16:35:37 +0300
commit7d7a9fc1310a0ade8ea61c5eb4d8b29456f8d604 (patch)
treeb2d0b239465994b9db183a7473a3d638a804d590
parentc52f2944492590c59599b0663f05611320efe441 (diff)
downloadlinux-7d7a9fc1310a0ade8ea61c5eb4d8b29456f8d604.tar.xz
ARM: dts: microchip: sama7d65: add Cortex-A7 PMU node
Add the Performance Monitoring Unit (PMU) node with the appropriate compatible string and interrupt line so that perf and other PMU-based tooling can function correctly on this SoC. [root@SAMA7D65 ~]$ dmesg | grep -i pmu [ 1.487869] hw-perfevents: enabled with armv7_cortex_a7 PMU driver, 5 (8000000f) counters available [root@SAMA7D65 ~]$ perf list hw List of pre-defined events (to be used in -e or -M): branch-instructions OR branches [Hardware event] branch-misses [Hardware event] bus-cycles [Hardware event] cache-misses [Hardware event] cache-references [Hardware event] cpu-cycles OR cycles [Hardware event] instructions [Hardware event] Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20260324070927.1496-2-mihai.sain@microchip.com [claudiu.beznea: keep nodes alphanumerically sorted] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
-rw-r--r--arch/arm/boot/dts/microchip/sama7d65.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index 80cfdec42ec4..67253bbc08df 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -67,6 +67,11 @@
#size-cells = <1>;
};
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
soc {
compatible = "simple-bus";
ranges;