diff options
| author | Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> | 2026-03-04 16:48:30 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-03-04 19:24:54 +0300 |
| commit | 7bc48fcdf9e77bf68ef04af015d50df2a9acac00 (patch) | |
| tree | f6b75377c6d1b5909723979f9dcfaf7547d90f3f | |
| parent | dd5b76257b4048151006620c9895e2f5f0d997eb (diff) | |
| download | linux-7bc48fcdf9e77bf68ef04af015d50df2a9acac00.tar.xz | |
clk: qcom: dispcc-sm4450: Fix DSI byte clock rate setting
The clock tree for byte_clk_src is as follows:
┌──────byte0_clk_src─────┐
│ │
byte0_clk byte0_div_clk_src
│
byte0_intf_clk
If both of its direct children have CLK_SET_RATE_PARENT with different
requests, byte0_clk_src (and its parent) will be reconfigured. In this
case, byte0_intf should strictly follow the rate of byte0_clk (with
some adjustments based on PHY mode).
Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.
Fixes: 76f05f1ec766 ("clk: qcom: Add DISPCC driver support for SM4450")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304-topic-dsi_byte_fixup-v1-4-b79b29f83176@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | drivers/clk/qcom/dispcc-sm4450.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/clk/qcom/dispcc-sm4450.c b/drivers/clk/qcom/dispcc-sm4450.c index e8752d01c8e6..2fdacc26df69 100644 --- a/drivers/clk/qcom/dispcc-sm4450.c +++ b/drivers/clk/qcom/dispcc-sm4450.c @@ -335,7 +335,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_regmap_div_ops, }, }; |