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| author | Konrad Dybcio <quic_kdybcio@quicinc.com> | 2024-09-19 01:57:14 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-10-06 05:52:55 +0300 |
| commit | 7a52db70c8c5f4e2f6cf404b6cac10beae43f2bd (patch) | |
| tree | e759cd4c19d1e01262f5225c417a81f1ab357fde | |
| parent | c17818a429affa1bc7c755e67e236c628c4099aa (diff) | |
| download | linux-7a52db70c8c5f4e2f6cf404b6cac10beae43f2bd.tar.xz | |
arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-1-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 642ca8f0236b..1dd760e97794 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1412,6 +1412,7 @@ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; }; intc: interrupt-controller@17200000 { |