diff options
| author | Leo Liu <leo.liu@amd.com> | 2017-02-07 19:47:12 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-05-25 00:41:30 +0300 |
| commit | 7741cced67aed83d87152a601d58bfb16eda8301 (patch) | |
| tree | f6c7461aa65253e9d330b534aa9ad87aa630a309 | |
| parent | 8c303c019014afe5842bf4001b4d762f05b3a77e (diff) | |
| download | linux-7741cced67aed83d87152a601d58bfb16eda8301.tar.xz | |
drm/amdgpu: expose vcn RB command
Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 |
2 files changed, 11 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index 937c6d93089f..5dbc6aa33917 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -30,6 +30,13 @@ #define AMDGPU_VCN_FIRMWARE_OFFSET 256 #define AMDGPU_VCN_MAX_ENC_RINGS 3 +#define VCN_CMD_FENCE 0x00000000 +#define VCN_CMD_TRAP 0x00000001 +#define VCN_CMD_WRITE_REG 0x00000004 +#define VCN_CMD_REG_READ_COND_WAIT 0x00000006 +#define VCN_CMD_PACKET_START 0x0000000a +#define VCN_CMD_PACKET_END 0x0000000b + struct amdgpu_vcn { struct amdgpu_bo *vcpu_bo; void *cpu_addr; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 9cd6690c6a3f..643e4cecc3f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -512,7 +512,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); - amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, VCN_CMD_FENCE << 1); amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); @@ -522,7 +522,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); - amdgpu_ring_write(ring, 2); + amdgpu_ring_write(ring, VCN_CMD_TRAP << 1); } /** @@ -576,7 +576,7 @@ static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring, amdgpu_ring_write(ring, data1); amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); - amdgpu_ring_write(ring, 8); + amdgpu_ring_write(ring, VCN_CMD_WRITE_REG << 1); } static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, @@ -593,7 +593,7 @@ static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, amdgpu_ring_write(ring, mask); amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); - amdgpu_ring_write(ring, 12); + amdgpu_ring_write(ring, VCN_CMD_REG_READ_COND_WAIT << 1); } static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, |