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authorIdo Reis <idor@ti.com>2012-04-22 21:45:52 +0400
committerLuciano Coelho <coelho@ti.com>2012-06-07 19:10:52 +0400
commit73395a79df00c3e0101bd7a0229dbbcc065b606a (patch)
tree8554dd79e3160f20f92a8d278bde9456a06c70ae
parent4085f641e704b1ff1a60f62756f49281a181f707 (diff)
downloadlinux-73395a79df00c3e0101bd7a0229dbbcc065b606a.tar.xz
wl18xx: support PG2 version of the chip
PG2 has a unique chip id. It supports similar HW quirks. Signed-off-by: Ido Reis <idor@ti.com> Signed-off-by: Arik Nemtsov <arik@wizery.com> Signed-off-by: Luciano Coelho <coelho@ti.com>
-rw-r--r--drivers/net/wireless/ti/wl18xx/main.c12
-rw-r--r--drivers/net/wireless/ti/wl18xx/reg.h1
2 files changed, 12 insertions, 1 deletions
diff --git a/drivers/net/wireless/ti/wl18xx/main.c b/drivers/net/wireless/ti/wl18xx/main.c
index e030b1297a2b..57b4a1089d0d 100644
--- a/drivers/net/wireless/ti/wl18xx/main.c
+++ b/drivers/net/wireless/ti/wl18xx/main.c
@@ -588,6 +588,17 @@ static int wl18xx_identify_chip(struct wl1271 *wl)
int ret = 0;
switch (wl->chip.id) {
+ case CHIP_ID_185x_PG20:
+ wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
+ wl->chip.id);
+ wl->sr_fw_name = WL18XX_FW_NAME;
+ /* wl18xx uses the same firmware for PLT */
+ wl->plt_fw_name = WL18XX_FW_NAME;
+ wl->quirks |= WLCORE_QUIRK_NO_ELP |
+ WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
+ WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;
+
+ break;
case CHIP_ID_185x_PG10:
wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)",
wl->chip.id);
@@ -602,7 +613,6 @@ static int wl18xx_identify_chip(struct wl1271 *wl)
/* PG 1.0 has some problems with MCS_13, so disable it */
wl->ht_cap[IEEE80211_BAND_2GHZ].mcs.rx_mask[1] &= ~BIT(5);
- /* TODO: need to blocksize alignment for RX/TX separately? */
break;
default:
wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
diff --git a/drivers/net/wireless/ti/wl18xx/reg.h b/drivers/net/wireless/ti/wl18xx/reg.h
index 43863d35feb2..e81f60913e88 100644
--- a/drivers/net/wireless/ti/wl18xx/reg.h
+++ b/drivers/net/wireless/ti/wl18xx/reg.h
@@ -140,6 +140,7 @@
#define WL18XX_FW_STATUS_ADDR 0x50F8
#define CHIP_ID_185x_PG10 (0x06030101)
+#define CHIP_ID_185x_PG20 (0x06030111)
/*
* Host Command Interrupt. Setting this bit masks