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| author | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2026-01-22 02:42:58 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-01-27 15:46:17 +0300 |
| commit | 6ffdc7eb48bd2268c37c2accad454c043b9cc987 (patch) | |
| tree | b41a3e8756823cf6b232d3738176a5fa412b1660 | |
| parent | dccc66b0e92d48d9a1908a3ccb8142e0ee3381f5 (diff) | |
| download | linux-6ffdc7eb48bd2268c37c2accad454c043b9cc987.tar.xz | |
regcache: Demote defaults readback from HW to debug print
Since commit 632e04739c8f ("clk: rs9: Fix suspend/resume"), the
clk-renesas-pcie-9series driver produces the following print in
kernel log on boot:
"
clk-renesas-pcie-9series 8-0068: No cache defaults, reading back from HW
"
This is caused by the presence of .num_reg_defaults_raw in its struct
regmap_config, without a matching .reg_defaults_raw table of built-in
register default values.
This configuration is valid, and causes the regcache code to read the
default register settings from the hardware, which is a valid behavior
for this particular chip. In fact, this configuration is more common
than configuration with .reg_defaults_raw built-in register defaults.
Do not warn about the read of default values being read from hardware,
as that is too strong and seems unnecessary, turn the warning into a
debug print.
Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/20260121234309.178391-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | drivers/base/regmap/regcache.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index 319c342bf5a0..a4e8983a5c6f 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -73,7 +73,7 @@ static int regcache_hw_init(struct regmap *map) if (!map->reg_defaults_raw) { bool cache_bypass = map->cache_bypass; - dev_warn(map->dev, "No cache defaults, reading back from HW\n"); + dev_dbg(map->dev, "No cache defaults, reading back from HW\n"); /* Bypass the cache access till data read from HW */ map->cache_bypass = true; |
