diff options
| author | mike.travis@hpe.com <mike.travis@hpe.com> | 2017-10-12 19:32:05 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2017-10-16 23:50:37 +0300 |
| commit | 6c66350d0a482892793b888b07c1177fc6d4b344 (patch) | |
| tree | 8fedc0ec845df896ee11b0fa0715bf4fb8d8fb2a | |
| parent | 41e7864ab5ce4ec36e89a9f55d8d9dfe19b0392c (diff) | |
| download | linux-6c66350d0a482892793b888b07c1177fc6d4b344.tar.xz | |
x86/tsc: Provide a means to disable TSC ART
On systems where multiple chassis are reset asynchronously, and thus
the TSC counters are started asynchronously, the offset needed to
convert to TSC to ART would be different. Disable ART in that case
and rely on the TSC counters to supply the accurate time.
Signed-off-by: Mike Travis <mike.travis@hpe.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Prarit Bhargava <prarit@redhat.com>
Cc: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Cc: Russ Anderson <russ.anderson@hpe.com>
Cc: Andrew Banman <andrew.banman@hpe.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Bin Gao <bin.gao@linux.intel.com>
Link: https://lkml.kernel.org/r/20171012163202.289397994@stormcage.americas.sgi.com
| -rw-r--r-- | arch/x86/kernel/tsc.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 896dbe31b407..f1326c0422c1 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -962,10 +962,14 @@ static void detect_art(void) if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) return; - /* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required */ + /* + * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required, + * and the TSC counter resets must not occur asynchronously. + */ if (boot_cpu_has(X86_FEATURE_HYPERVISOR) || !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) || - !boot_cpu_has(X86_FEATURE_TSC_ADJUST)) + !boot_cpu_has(X86_FEATURE_TSC_ADJUST) || + tsc_async_resets) return; cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator, |