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| author | Fabien Parent <fparent@baylibre.com> | 2019-03-24 00:16:01 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-04-26 00:35:29 +0300 |
| commit | 699480d062e06b174ee8aabd094b084deb2688b2 (patch) | |
| tree | 2a063ec7a8bc5da845cb93bbe385062cb89abba4 | |
| parent | eb2814bc60d93ef65b0e0f6db456b4f58ff02a06 (diff) | |
| download | linux-699480d062e06b174ee8aabd094b084deb2688b2.tar.xz | |
dt-bindings: mediatek: apmixedsys: add support for MT8516
Add binding documentation of apmixedsys for MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/mt8516-clk.h | 10 |
2 files changed, 11 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index 9adf28d0141b..161e63a6c254 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -15,6 +15,7 @@ Required Properties: - "mediatek,mt8135-apmixedsys" - "mediatek,mt8173-apmixedsys" - "mediatek,mt8183-apmixedsys", "syscon" + - "mediatek,mt8516-apmixedsys" - #clock-cells: Must be 1 The apmixedsys controller uses the common clk binding from diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h index 956ee2c0748e..9cfca53cd78d 100644 --- a/include/dt-bindings/clock/mt8516-clk.h +++ b/include/dt-bindings/clock/mt8516-clk.h @@ -8,6 +8,16 @@ #ifndef _DT_BINDINGS_CLK_MT8516_H #define _DT_BINDINGS_CLK_MT8516_H +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MMPLL 3 +#define CLK_APMIXED_APLL1 4 +#define CLK_APMIXED_APLL2 5 +#define CLK_APMIXED_NR_CLK 6 + /* INFRACFG */ #define CLK_IFR_MUX1_SEL 0 |