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| author | Sandipan Das <sandipan.das@amd.com> | 2025-12-06 03:16:49 +0300 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2025-12-17 15:31:07 +0300 |
| commit | 65eb3a9a8a34fa9188e0ab5e657d84ce4fa242a7 (patch) | |
| tree | b8c9f649a3a2ed19a12edd94623cb16ce1d7e4c1 | |
| parent | 4280d79587a3fd4bf9415705536fe385467c5f44 (diff) | |
| download | linux-65eb3a9a8a34fa9188e0ab5e657d84ce4fa242a7.tar.xz | |
perf/x86/amd: Support PERF_PMU_CAP_MEDIATED_VPMU for AMD host
Apply the PERF_PMU_CAP_MEDIATED_VPMU flag for version 2 and later
implementations of the core PMU. Aside from having Global Control and
Status registers, virtualizing the PMU using the mediated model requires
an interface to set or clear the overflow bits in the Global Status MSRs
while restoring or saving the PMU context of a vCPU.
PerfMonV2-capable hardware has additional MSRs for this purpose, namely
PerfCntrGlobalStatusSet and PerfCntrGlobalStatusClr, thereby making it
suitable for use with mediated vPMU.
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Mingwei Zhang <mizhang@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Xudong Hao <xudong.hao@intel.com>
Link: https://patch.msgid.link/20251206001720.468579-14-seanjc@google.com
| -rw-r--r-- | arch/x86/events/amd/core.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 44656d2fb555..0c92ed5f464b 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -1439,6 +1439,8 @@ static int __init amd_core_pmu_init(void) amd_pmu_global_cntr_mask = x86_pmu.cntr_mask64; + x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_MEDIATED_VPMU; + /* Update PMC handling functions */ x86_pmu.enable_all = amd_pmu_v2_enable_all; x86_pmu.disable_all = amd_pmu_v2_disable_all; |