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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2025-11-03 23:03:47 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2026-01-05 16:37:17 +0300
commit6569dced2b98fc44c55640efc735d301eeac2387 (patch)
tree7de898ffb08381338de89ff24b765fd911f3d61e
parent71270e792c72da7c0078a0af67f7f15aa24c1403 (diff)
downloadlinux-6569dced2b98fc44c55640efc735d301eeac2387.tar.xz
arm64: dts: renesas: r9a09g056: Add FCPV and VSPD nodes
Add FCPV and VSPD nodes to RZ/V2N SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251103200349.62087-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-rw-r--r--arch/arm64/boot/dts/renesas/r9a09g056.dtsi24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index 8781c2fa7313..dd0908e8c156 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -955,6 +955,30 @@
};
};
};
+
+ fcpvd: fcp@16470000 {
+ compatible = "renesas,r9a09g056-fcpvd", "renesas,fcpv";
+ reg = <0 0x16470000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ };
+
+ vspd: vsp@16480000 {
+ compatible = "renesas,r9a09g056-vsp2", "renesas,r9a07g044-vsp2";
+ reg = <0 0x16480000 0 0x10000>;
+ interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ renesas,fcp = <&fcpvd>;
+ };
};
stmmac_axi_setup: stmmac-axi-config {