diff options
| author | Marc Zyngier <maz@kernel.org> | 2025-11-25 19:01:44 +0300 |
|---|---|---|
| committer | Oliver Upton <oupton@kernel.org> | 2025-11-26 09:23:01 +0300 |
| commit | 64d67e7add109bfc54eac454558a4355af879ba7 (patch) | |
| tree | a3fb6cf8816685ee5d03dadbbb7d163101387573 | |
| parent | de8842327728d07b5d836688a66ae5fa56902527 (diff) | |
| download | linux-64d67e7add109bfc54eac454558a4355af879ba7.tar.xz | |
KVM: arm64: Convert ICH_HCR_EL2_TDIR cap to EARLY_LOCAL_CPU_FEATURE
Suzuki notices that making the ICH_HCR_EL2_TDIR capability a system
one isn't a very good idea, should we end-up with CPUs that have
asymmetric TDIR support (somehow unlikely, but you never know what
level of stupidity vendors are up to). For this hypothetical setup,
making this an "EARLY_LOCAL_CPU_FEATURE" is a much better option.
This is actually consistent with what we already do with GICv5
legacy interface, so flip the capability over.
Reported-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Fixes: 2a28810cbb8b2 ("KVM: arm64: GICv3: Detect and work around the lack of ICV_DIR_EL1 trapping")
Link: https://lore.kernel.org/r/5df713d4-8b79-4456-8fd1-707ca89a61b6@arm.com
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://msgid.link/20251125160144.1086511-1-maz@kernel.org
Signed-off-by: Oliver Upton <oupton@kernel.org>
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 5de51cb1b8fe..75fb9a0efcc8 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2325,14 +2325,14 @@ static bool can_trap_icv_dir_el1(const struct arm64_cpu_capabilities *entry, BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV3_CPUIF); BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV5_LEGACY); - if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF) && + if (!this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF) && !is_midr_in_range_list(has_vgic_v3)) return false; if (!is_hyp_mode_available()) return false; - if (cpus_have_cap(ARM64_HAS_GICV5_LEGACY)) + if (this_cpu_has_cap(ARM64_HAS_GICV5_LEGACY)) return true; if (is_kernel_in_hyp_mode()) @@ -2863,7 +2863,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { */ .desc = "ICV_DIR_EL1 trapping", .capability = ARM64_HAS_ICH_HCR_EL2_TDIR, - .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, .matches = can_trap_icv_dir_el1, }, #ifdef CONFIG_ARM64_E0PD |