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| author | Janne Grunau <j@jannau.net> | 2023-02-14 13:38:01 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2023-03-27 17:15:14 +0300 |
| commit | 640a3b7a3d138cb2467b75a6830144fac1c26a81 (patch) | |
| tree | bf7fd9fb2e606d923acae9eae3287ee532ff8eb9 | |
| parent | 16e15834659e9f5c05b9f12da6e86d76165c60a3 (diff) | |
| download | linux-640a3b7a3d138cb2467b75a6830144fac1c26a81.tar.xz | |
dt-bindings: arm-pmu: Add PMU compatible strings for Apple M2 cores
The PMUs on the Apple M2 cores avalanche and blizzard CPU are compatible
with M1 ones. As on M1 we don't know exactly what the counters count so
use a distinct compatible for each micro-architecture.
Apple's PMU counter description omits a counter for M2 so there
is some variation on the interpretation of the counters.
Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Hector Martin <marcan@marcan.st>
Link: https://lore.kernel.org/r/20230214-apple_m2_pmu-v1-1-9c9213ab9b63@jannau.net
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/arm/pmu.yaml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index dbb6f3dc5ae5..e14358bf0b9c 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,6 +20,8 @@ properties: items: - enum: - apm,potenza-pmu + - apple,avalanche-pmu + - apple,blizzard-pmu - apple,firestorm-pmu - apple,icestorm-pmu - arm,armv8-pmuv3 # Only for s/w models |