diff options
| author | Brajesh Gupta <brajesh.gupta@imgtec.com> | 2026-03-13 09:38:25 +0300 |
|---|---|---|
| committer | Matt Coster <matt.coster@imgtec.com> | 2026-03-23 18:02:05 +0300 |
| commit | 62a6f98cda4ec75107e96571346349a649fc63d1 (patch) | |
| tree | 6ce80c624df396466195a390972bb7c8520dfcc1 | |
| parent | 51e39ceeca7e85a3b9ca533502a404eb5f3b0f02 (diff) | |
| download | linux-62a6f98cda4ec75107e96571346349a649fc63d1.tar.xz | |
drm/imagination: Skip 2nd thread DM association for non META Firmware
Only a META firmware can have two threads.
Signed-off-by: Brajesh Gupta <brajesh.gupta@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-2-9e3c251d278e@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
| -rw-r--r-- | drivers/gpu/drm/imagination/pvr_fw_startstop.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c index 6ae0489f7e2e..e24ed6fc4362 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c +++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c @@ -243,12 +243,15 @@ pvr_fw_stop(struct pvr_device *pvr_dev) pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL & ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK); - pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, - ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & - ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); - pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, - ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & - ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); + + if (meta_fw) { + pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, + ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & + ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); + pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, + ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & + ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); + } /* Extra Idle checks. */ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0, |