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| author | Aapo Vienamo <avienamo@nvidia.com> | 2018-08-10 21:14:03 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-08-27 13:27:35 +0300 |
| commit | 5879600a70d07d643f1b858f3f94675a9e93ba29 (patch) | |
| tree | c2b908a8de82a4db9ecddd3f4490ddfd99a06671 | |
| parent | 98a2494f847c2d219db3b6460a3446199f0bd300 (diff) | |
| download | linux-5879600a70d07d643f1b858f3f94675a9e93ba29.tar.xz | |
arm64: dts: tegra210: Add SDMMC4 DQS trim value
Add the HS400 DQS trim value for Tegra210 SDMMC4.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 14da98ac65e8..f8e5f0908ade 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1115,6 +1115,7 @@ assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + nvidia,dqs-trim = <40>; status = "disabled"; }; |