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| author | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2025-12-05 18:34:42 +0300 |
|---|---|---|
| committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2026-03-02 14:20:15 +0300 |
| commit | 5548e8a4663d9decc8215c53e4a41c704f183cbb (patch) | |
| tree | 5fe0ee4ea824545f0b3394c6be95d8a7eded9c47 | |
| parent | 9c46fcaf2efa78e814e102c5828cf5c825a133ec (diff) | |
| download | linux-5548e8a4663d9decc8215c53e4a41c704f183cbb.tar.xz | |
ARM: use BIT() and GENMASK() for fault status register fields
Modernise the fault status field definitions by using BIT() and
GENMASK().
Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
| -rw-r--r-- | arch/arm/mm/fault.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h index e95f44757dc9..d2bdedaefe14 100644 --- a/arch/arm/mm/fault.h +++ b/arch/arm/mm/fault.h @@ -5,12 +5,12 @@ /* * Fault status register encodings. We steal bit 31 for our own purposes. */ -#define FSR_LNX_PF (1 << 31) -#define FSR_CM (1 << 13) -#define FSR_WRITE (1 << 11) -#define FSR_FS4 (1 << 10) -#define FSR_FS3_0 (15) -#define FSR_FS5_0 (0x3f) +#define FSR_LNX_PF BIT(31) +#define FSR_CM BIT(13) +#define FSR_WRITE BIT(11) +#define FSR_FS4 BIT(10) +#define FSR_FS3_0 GENMASK(3, 0) +#define FSR_FS5_0 GENMASK(5, 0) #ifdef CONFIG_ARM_LPAE #define FSR_FS_AEA 17 |