diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-02-12 02:19:33 +0300 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@linux.intel.com> | 2025-03-04 17:39:32 +0300 |
| commit | 50c82997627b899f05a541f8858a8f34d8bf4bc7 (patch) | |
| tree | 22fe30309d84fb4a3c9de25967be9b9f56153c0e | |
| parent | 66ec4c1ab1c1c6b90afba0dd5ece625009c2c9ab (diff) | |
| download | linux-50c82997627b899f05a541f8858a8f34d8bf4bc7.tar.xz | |
drm/i915: Introduce RING_FAULT_VADDR_MASK
Add a proper bitmask definition for the pre-bdw fault
virtual address bits insted of abusing PAGE_MASK.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-6-ville.syrjala@linux.intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt.c | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 |
2 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 04b43852a397..b8189754edb7 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -302,17 +302,19 @@ static void gen6_check_faults(struct intel_gt *gt) { struct intel_engine_cs *engine; enum intel_engine_id id; - unsigned long fault; for_each_engine(engine, gt, id) { + u32 fault; + fault = GEN6_RING_FAULT_REG_READ(engine); + if (fault & RING_FAULT_VALID) { gt_dbg(gt, "Unexpected fault\n" - "\tAddr: 0x%08lx\n" + "\tAddr: 0x%08x\n" "\tAddress space: %s\n" "\tSource ID: %d\n" "\tType: %d\n", - fault & PAGE_MASK, + fault & RING_FAULT_VADDR_MASK, fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault), diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index e550d4f9c3e6..06907b5fca09 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -326,6 +326,7 @@ _RING_FAULT_REG_VCS, \ _RING_FAULT_REG_VECS, \ _RING_FAULT_REG_BCS)) +#define RING_FAULT_VADDR_MASK REG_GENMASK(31, 12) /* pre-bdw */ #define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12) /* bdw+ */ #define RING_FAULT_GTTSEL_MASK REG_BIT(11) /* pre-bdw */ #define RING_FAULT_SRCID_MASK REG_GENMASK(10, 3) |