summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2026-01-23 19:04:05 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2026-01-23 19:04:05 +0300
commit4f423d896f13e989deff8b655c81232759920dcf (patch)
treecadca27e0d951569d08c9601dac0a4dc446e7072
parenteb89b17f283b233ba721fce358fa0d15223ae69d (diff)
parentae801944cbfb70326afc373c11a282d1ce3bae97 (diff)
downloadlinux-4f423d896f13e989deff8b655c81232759920dcf.tar.xz
Merge tag 'fpga-for-v6.20-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga into char-misc-next
Xu writes: FPGA Manager changes for 6.20-rc1 - Mukesh fixes a typo in comments. - Thadeu adds support for built-in dfl driver. - Michal changes his email. - Romain corrects the error handling when an fpga bridge is missing. All patches have been reviewed on the mailing list, and have been in the last linux-next releases (as part of our for-next branch). Signed-off-by: Xu Yilun <yilun.xu@intel.com> * tag 'fpga-for-v6.20-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga: fpga: dfl: fix typo in header file fpga: dfl: use subsys_initcall to allow built-in drivers to be added fpga: xilinx: Switch Michal Simek's email to new one fpga: of-fpga-region: Fail if any bridge is missing
-rw-r--r--drivers/fpga/dfl.c2
-rw-r--r--drivers/fpga/dfl.h2
-rw-r--r--drivers/fpga/of-fpga-region.c8
-rw-r--r--drivers/fpga/xilinx-pr-decoupler.c2
-rw-r--r--drivers/fpga/zynq-fpga.c2
5 files changed, 8 insertions, 8 deletions
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index 7022657243c0..449c3a082e23 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -2018,7 +2018,7 @@ static void __exit dfl_fpga_exit(void)
bus_unregister(&dfl_bus_type);
}
-module_init(dfl_fpga_init);
+subsys_initcall(dfl_fpga_init);
module_exit(dfl_fpga_exit);
MODULE_DESCRIPTION("FPGA Device Feature List (DFL) Support");
diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
index 95539f1213cb..9549f63b00eb 100644
--- a/drivers/fpga/dfl.h
+++ b/drivers/fpga/dfl.h
@@ -82,7 +82,7 @@
#define DFH_TYPE_FIU 4
/*
- * DFHv1 Register Offset definitons
+ * DFHv1 Register Offset definitions
* In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA
* as common header registers
*/
diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c
index 43db4bb77138..caa091224dc5 100644
--- a/drivers/fpga/of-fpga-region.c
+++ b/drivers/fpga/of-fpga-region.c
@@ -83,7 +83,7 @@ static struct fpga_manager *of_fpga_region_get_mgr(struct device_node *np)
* done with the bridges.
*
* Return: 0 for success (even if there are no bridges specified)
- * or -EBUSY if any of the bridges are in use.
+ * or an error code if any of the bridges are not available.
*/
static int of_fpga_region_get_bridges(struct fpga_region *region)
{
@@ -130,10 +130,10 @@ static int of_fpga_region_get_bridges(struct fpga_region *region)
&region->bridge_list);
of_node_put(br);
- /* If any of the bridges are in use, give up */
- if (ret == -EBUSY) {
+ /* If any of the bridges are not available, give up */
+ if (ret) {
fpga_bridges_put(&region->bridge_list);
- return -EBUSY;
+ return ret;
}
}
diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx-pr-decoupler.c
index 822751fad18a..6994d68e9036 100644
--- a/drivers/fpga/xilinx-pr-decoupler.c
+++ b/drivers/fpga/xilinx-pr-decoupler.c
@@ -173,5 +173,5 @@ module_platform_driver(xlnx_pr_decoupler_driver);
MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");
-MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
+MODULE_AUTHOR("Michal Simek <michal.simek@amd.com>");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
index b7629a0e4813..9d1d599ef718 100644
--- a/drivers/fpga/zynq-fpga.c
+++ b/drivers/fpga/zynq-fpga.c
@@ -652,6 +652,6 @@ static struct platform_driver zynq_fpga_driver = {
module_platform_driver(zynq_fpga_driver);
MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
-MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
+MODULE_AUTHOR("Michal Simek <michal.simek@amd.com>");
MODULE_DESCRIPTION("Xilinx Zynq FPGA Manager");
MODULE_LICENSE("GPL v2");