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authorJakub Kicinski <kuba@kernel.org>2025-10-23 04:08:06 +0300
committerJakub Kicinski <kuba@kernel.org>2025-10-23 04:16:17 +0300
commit4c3aa496a2faac77069ea041e886edff01639610 (patch)
tree046942f62337c8ec17658909d5cec4b2a0b82d1a
parentd63f0391d6c7b75e1a847e1a26349fa8cad0004d (diff)
parent706136c5723626fcde8dd8f598a4dcd251e24927 (diff)
downloadlinux-4c3aa496a2faac77069ea041e886edff01639610.tar.xz
Merge branch 'net-ravb-fix-soc-specific-configuration-and-descriptor-handling-issues'
Lad Prabhakar says: ==================== net: ravb: Fix SoC-specific configuration and descriptor handling issues [part] This series addresses several issues in the Renesas Ethernet AVB (ravb) driver related descriptor ordering. A potential ordering hazard in descriptor setup could cause the DMA engine to start prematurely, leading to TX stalls on some platforms. The series includes the following changes: Enforce descriptor type ordering to prevent early DMA start Ensure proper write ordering of TX descriptor type fields to prevent the DMA engine from observing an incomplete descriptor chain. This fixes observed TX stalls on RZ/G2L platforms running RT kernels. Tested on R/G1x Gen2, RZ/G2x Gen3 and RZ/G2L family hardware. ==================== Link: https://patch.msgid.link/20251017151830.171062-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
-rw-r--r--drivers/net/ethernet/renesas/ravb_main.c24
1 files changed, 22 insertions, 2 deletions
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index 9d3bd65b85ff..e2d7ce1a85e8 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -2211,15 +2211,35 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
skb_tx_timestamp(skb);
}
- /* Descriptor type must be set after all the above writes */
- dma_wmb();
+
if (num_tx_desc > 1) {
desc->die_dt = DT_FEND;
desc--;
+ /* When using multi-descriptors, DT_FEND needs to get written
+ * before DT_FSTART, but the compiler may reorder the memory
+ * writes in an attempt to optimize the code.
+ * Use a dma_wmb() barrier to make sure DT_FEND and DT_FSTART
+ * are written exactly in the order shown in the code.
+ * This is particularly important for cases where the DMA engine
+ * is already running when we are running this code. If the DMA
+ * sees DT_FSTART without the corresponding DT_FEND it will enter
+ * an error condition.
+ */
+ dma_wmb();
desc->die_dt = DT_FSTART;
} else {
+ /* Descriptor type must be set after all the above writes */
+ dma_wmb();
desc->die_dt = DT_FSINGLE;
}
+
+ /* Before ringing the doorbell we need to make sure that the latest
+ * writes have been committed to memory, otherwise it could delay
+ * things until the doorbell is rang again.
+ * This is in replacement of the read operation mentioned in the HW
+ * manuals.
+ */
+ dma_wmb();
ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
priv->cur_tx[q] += num_tx_desc;