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| author | Ryan Wanner <Ryan.Wanner@microchip.com> | 2025-04-15 00:41:27 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2025-05-16 08:31:29 +0300 |
| commit | 4b3d951f288c2ae4f082f13b22899ed190156a65 (patch) | |
| tree | e56bd5cf9dcedd17e592b7970cd7d86263cd2011 | |
| parent | f5b56abe58b06c5882d0f00f53bfe5073462f694 (diff) | |
| download | linux-4b3d951f288c2ae4f082f13b22899ed190156a65.tar.xz | |
ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC
Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able
to store the RTT time data.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/e8868ef06102241b47883ba10edaed751831be6d.1744666011.git.Ryan.Wanner@microchip.com
[claudiu.beznea: keep nodes sorted by their address]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
| -rw-r--r-- | arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index f93978e98ac2..d08d773b1cc5 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -132,6 +132,13 @@ status = "disabled"; }; + rtt: rtc@e001d300 { + compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; + reg = <0xe001d300 0x30>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk32k 0>; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>; @@ -139,6 +146,11 @@ #clock-cells = <1>; }; + gpbr: syscon@e001d700 { + compatible = "microchip,sama7d65-gpbr", "syscon"; + reg = <0xe001d700 0x48>; + }; + rtc: rtc@e001d800 { compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; reg = <0xe001d800 0x30>; |