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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-04-22 12:37:21 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-04-22 12:37:21 +0300 |
| commit | 4902413495884824f42ec405c019d49531987f1c (patch) | |
| tree | a6df39de892c1ce35480fdb7ed58558480dd891d | |
| parent | ef224dd26ca3554ba810996710bcf671bc1c6be9 (diff) | |
| parent | ad227dab306543208a0658357a82712e678a06f4 (diff) | |
| download | linux-4902413495884824f42ec405c019d49531987f1c.tar.xz | |
Merge tag 'renesas-r9a09g057-dt-binding-defs-tag3' into renesas-clk-for-v6.16
Renesas RZ/V2H USB2 and GBETH Clock DT Binding Definitions
USB2 and Gigabit Ethernet clock DT binding definitions for the Renesas
RZ/V2H (R9A09G057) SoC, shared by driver and DT source files.
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g057-cpg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h index 541e6d719bd6..884dbeb1e139 100644 --- a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h +++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h @@ -17,5 +17,9 @@ #define R9A09G057_CM33_CLK0 6 #define R9A09G057_CST_0_SWCLKTCK 7 #define R9A09G057_IOTOP_0_SHCLK 8 +#define R9A09G057_USB2_0_CLK_CORE0 9 +#define R9A09G057_USB2_0_CLK_CORE1 10 +#define R9A09G057_GBETH_0_CLK_PTP_REF_I 11 +#define R9A09G057_GBETH_1_CLK_PTP_REF_I 12 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */ |