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authorMatt Roper <matthew.d.roper@intel.com>2023-12-14 21:47:05 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-21 19:46:16 +0300
commit48e70d2a1a9c8d58c48b2840feda3aa3bc330a94 (patch)
tree00e4ca28c3d8808bbda3a21fef9242978e7e296f
parentf52e4e9065786dd20477879d834c5c33a3ae9498 (diff)
downloadlinux-48e70d2a1a9c8d58c48b2840feda3aa3bc330a94.tar.xz
drm/xe: Move GSC HECI base offsets out of register header
These offsets are only used to setup the auxiliary device BAR information and are never used for driver read/write operations. Move them to the GSC HECI file where they're actually used. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20231214184659.2249559-15-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-rw-r--r--drivers/gpu/drm/xe/regs/xe_regs.h4
-rw-r--r--drivers/gpu/drm/xe/xe_heci_gsc.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index b7d3b42ec003..67ce087e21d0 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -7,10 +7,6 @@
#include "regs/xe_reg_defs.h"
-#define DG1_GSC_HECI2_BASE 0x00259000
-#define PVC_GSC_HECI2_BASE 0x00285000
-#define DG2_GSC_HECI2_BASE 0x00374000
-
#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
#define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8)
#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4)
diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_gsc.c
index d8e982e3d9a2..19eda00d5cc4 100644
--- a/drivers/gpu/drm/xe/xe_heci_gsc.c
+++ b/drivers/gpu/drm/xe/xe_heci_gsc.c
@@ -16,6 +16,10 @@
#define GSC_BAR_LENGTH 0x00000FFC
+#define DG1_GSC_HECI2_BASE 0x259000
+#define PVC_GSC_HECI2_BASE 0x285000
+#define DG2_GSC_HECI2_BASE 0x374000
+
static void heci_gsc_irq_mask(struct irq_data *d)
{
/* generic irq handling */