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authorJim Lin <jilin@nvidia.com>2012-09-18 12:42:17 +0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-09-18 20:40:56 +0400
commit45c2da62199bcea380273b2fba7fa16c1ff27a30 (patch)
treeccd818cee315c8fd64a7c3c536be9cb4e5dcfafc
parent8d733e26c076f47e7774c0e5baa74c9b1c01199a (diff)
downloadlinux-45c2da62199bcea380273b2fba7fa16c1ff27a30.tar.xz
USB: EHCI: Tegra: Fix wrong register definition
Fix the issue that EHCI registers, hostpc[0] and usbmode_ex, are not correctly accessed on Tegra3 platform. Signed-off-by: Jim Lin <jilin@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--include/linux/usb/ehci_def.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/linux/usb/ehci_def.h b/include/linux/usb/ehci_def.h
index 9a446302b658..daec99af5d54 100644
--- a/include/linux/usb/ehci_def.h
+++ b/include/linux/usb/ehci_def.h
@@ -171,18 +171,18 @@ struct ehci_regs {
#define USBMODE_CM_HC (3<<0) /* host controller mode */
#define USBMODE_CM_IDLE (0<<0) /* idle state */
- u32 reserved4[7];
+ u32 reserved4[6];
/* Moorestown has some non-standard registers, partially due to the fact that
* its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
* PORTSCx
*/
/* HOSTPC: offset 0x84 */
- u32 hostpc[0]; /* HOSTPC extension */
+ u32 hostpc[1]; /* HOSTPC extension */
#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
#define HOSTPC_PSPD (3<<25) /* Port speed detection */
- u32 reserved5[17];
+ u32 reserved5[16];
/* USBMODE_EX: offset 0xc8 */
u32 usbmode_ex; /* USB Device mode extension */