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| author | Jakub Kicinski <kuba@kernel.org> | 2026-03-19 05:05:16 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2026-03-19 05:05:17 +0300 |
| commit | 4455a30b043ac2e20369b400a2132aaf127735e3 (patch) | |
| tree | c7e3c0d258cf55e81bdf53d5db903a507ce38cf8 | |
| parent | 2839841f8e8fb18392c0a4a3e96bb597c9bccbfb (diff) | |
| parent | 96aca5efec8a737057f31cd61586a4bb62af9829 (diff) | |
| download | linux-4455a30b043ac2e20369b400a2132aaf127735e3.tar.xz | |
Merge branch 'net-mlx5-support-ptm-on-arm-architecture'
Tariq Toukan says:
====================
net/mlx5: Support PTM on ARM architecture
This series by Carolina refactors mlx5 crosststamp initialization and
enables cross-timestamp support on ARM.
====================
Link: https://patch.msgid.link/20260316133607.8738-1-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c | 40 |
1 files changed, 26 insertions, 14 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index bd4e042077af..d785f1b4f2e1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -38,10 +38,10 @@ #include "lib/eq.h" #include "en.h" #include "clock.h" -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) || defined(CONFIG_ARM_ARCH_TIMER) #include <linux/timekeeping.h> #include <linux/cpufeature.h> -#endif /* CONFIG_X86 */ +#endif /* CONFIG_X86 || CONFIG_ARM_ARCH_TIMER */ #define MLX5_RT_CLOCK_IDENTITY_SIZE MLX5_FLD_SZ_BYTES(mrtcq_reg, rt_clock_identity) @@ -229,7 +229,7 @@ static int mlx5_set_mtutc(struct mlx5_core_dev *dev, u32 *mtutc, u32 size) MLX5_REG_MTUTC, 0, 1); } -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) || defined(CONFIG_ARM_ARCH_TIMER) static bool mlx5_is_ptm_source_time_available(struct mlx5_core_dev *dev) { u32 out[MLX5_ST_SZ_DW(mtptm_reg)] = {0}; @@ -275,7 +275,8 @@ static int mlx5_mtctr_read(struct mlx5_core_dev *mdev, host = MLX5_GET64(mtctr_reg, out, first_clock_timestamp); *sys_counterval = (struct system_counterval_t) { .cycles = host, - .cs_id = CSID_X86_ART, + .cs_id = IS_ENABLED(CONFIG_X86) ? CSID_X86_ART : + CSID_ARM_ARCH_COUNTER, .use_nsecs = true, }; *device = MLX5_GET64(mtctr_reg, out, second_clock_timestamp); @@ -373,7 +374,7 @@ unlock: mlx5_clock_unlock(clock); return err; } -#endif /* CONFIG_X86 */ +#endif /* CONFIG_X86 || CONFIG_ARM_ARCH_TIMER */ static u64 mlx5_read_time(struct mlx5_core_dev *dev, struct ptp_system_timestamp *sts, @@ -1301,6 +1302,25 @@ static void mlx5_init_timer_max_freq_adjustment(struct mlx5_core_dev *mdev) min(S32_MAX, 1 << log_max_freq_adjustment); } +static void mlx5_init_crosststamp(struct mlx5_core_dev *mdev, + bool expose_cycles, struct mlx5_clock *clock) +{ +#if defined(CONFIG_X86) + if (!boot_cpu_has(X86_FEATURE_ART)) + return; +#endif /* CONFIG_X86 */ +#if defined(CONFIG_X86) || defined(CONFIG_ARM_ARCH_TIMER) + if (!MLX5_CAP_MCAM_REG3(mdev, mtptm) || + !MLX5_CAP_MCAM_REG3(mdev, mtctr)) + return; + + clock->ptp_info.getcrosststamp = mlx5_ptp_getcrosststamp; + if (expose_cycles) + clock->ptp_info.getcrosscycles = mlx5_ptp_getcrosscycles; + +#endif /* CONFIG_X86 || CONFIG_ARM_ARCH_TIMER */ +} + static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) { struct mlx5_clock *clock = mdev->clock; @@ -1315,15 +1335,7 @@ static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) expose_cycles = !MLX5_CAP_GEN(mdev, disciplined_fr_counter) || !mlx5_real_time_mode(mdev); -#ifdef CONFIG_X86 - if (MLX5_CAP_MCAM_REG3(mdev, mtptm) && - MLX5_CAP_MCAM_REG3(mdev, mtctr) && boot_cpu_has(X86_FEATURE_ART)) { - clock->ptp_info.getcrosststamp = mlx5_ptp_getcrosststamp; - if (expose_cycles) - clock->ptp_info.getcrosscycles = - mlx5_ptp_getcrosscycles; - } -#endif /* CONFIG_X86 */ + mlx5_init_crosststamp(mdev, expose_cycles, clock); if (expose_cycles) clock->ptp_info.getcyclesx64 = mlx5_ptp_getcyclesx; |