diff options
| author | Zhanjun Dong <zhanjun.dong@intel.com> | 2023-07-06 20:47:04 +0300 |
|---|---|---|
| committer | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2023-07-12 19:27:43 +0300 |
| commit | 43aa755eae2cda71684f3f5fe40c00f728d25722 (patch) | |
| tree | 075846e68cb80f7bfc8a0e6f2a224241e7b51321 | |
| parent | 2f42c5afb34b5696cf5fe79e744f99be9b218798 (diff) | |
| download | linux-43aa755eae2cda71684f3f5fe40c00f728d25722.tar.xz | |
drm/i915/mtl: Update cache coherency setting for context structure
As context structure is shared memory for CPU/GPU, Wa_22016122933 is
needed for this memory block as well.
Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
CC: Fei Yang <fei.yang@intel.com>
Reviewed-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230706174704.177929-1-zhanjun.dong@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_lrc.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index a4ec20aaafe2..1b710102390b 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1092,8 +1092,15 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine) obj = i915_gem_object_create_lmem(engine->i915, context_size, I915_BO_ALLOC_PM_VOLATILE); - if (IS_ERR(obj)) + if (IS_ERR(obj)) { obj = i915_gem_object_create_shmem(engine->i915, context_size); + /* + * Wa_22016122933: For MTL the shared memory needs to be mapped + * as WC on CPU side and UC (PAT index 2) on GPU side + */ + if (IS_METEORLAKE(engine->i915)) + i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE); + } if (IS_ERR(obj)) return ERR_CAST(obj); |