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| author | Bjorn Helgaas <bhelgaas@google.com> | 2026-02-07 02:09:47 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2026-02-07 02:09:47 +0300 |
| commit | 42e8a4ef13dc9715ed06acb39e6973468061c89e (patch) | |
| tree | dec869b29ccb12a334f60ba7b88c10a8924ddb17 | |
| parent | a1dd5e7a30c163467622ed02e260e4928f3faf41 (diff) | |
| parent | b5d712e5b87fc56ff838684afb1bae359eb8069f (diff) | |
| download | linux-42e8a4ef13dc9715ed06acb39e6973468061c89e.tar.xz | |
Merge branch 'pci/controller/dwc-rockchip'
- Disable unused BAR 0 and BAR 1 for Root Port (Shawn Lin)
* pci/controller/dwc-rockchip:
PCI: dw-rockchip: Disable BAR 0 and BAR 1 for Root Port
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-dw-rockchip.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 03ad8c242366..5b17da63151d 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -85,6 +85,8 @@ #define PCIE_LINKUP_MASK GENMASK(17, 16) #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) +#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 + struct rockchip_pcie { struct dw_pcie pci; void __iomem *apb_base; @@ -312,6 +314,8 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) if (irq < 0) return irq; + pci->dbi_base2 = pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET; + ret = rockchip_pcie_init_irq_domain(rockchip); if (ret < 0) dev_err(dev, "failed to init irq domain\n"); @@ -322,6 +326,10 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) rockchip_pcie_configure_l1ss(pci); rockchip_pcie_enable_l0s(pci); + /* Disable Root Ports BAR0 and BAR1 as they report bogus size */ + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0); + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0); + return 0; } |