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authorStephen Boyd <sboyd@kernel.org>2026-04-12 02:24:53 +0300
committerStephen Boyd <sboyd@kernel.org>2026-04-12 02:24:53 +0300
commit42ca4f0c9444bea688c2f4797b00cea0b3f842d9 (patch)
tree3d6f5d63856e2d5cc32d858e3aaa0a819dddefe8
parentc369299895a591d96745d6492d4888259b004a9e (diff)
parente57c36bc1a3e459239ead492ebce731a88a264b1 (diff)
downloadlinux-42ca4f0c9444bea688c2f4797b00cea0b3f842d9.tar.xz
Merge tag 'samsung-clk-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clock driver updates from Krzysztof Kozlowski: - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock controllers on the SoC - ExynosAutov920: Add G3D (GPU) clock controller - Exynos850: Define missing clock for the APM mailbox * tag 'samsung-clk-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: exynos850: Add APM-to-AP mailbox clock dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock clk: samsung: Use %pe format to simplify clk: samsung: pll: Fix possible truncation in a9fraco recalc rate clk: samsung: exynosautov920: add block G3D clock support dt-bindings: clock: exynosautov920: add G3D clock definitions clk: samsung: gs101: harmonise symbol names (clock arrays) clk: samsung: artpec-9: Add initial clock support for ARTPEC-9 SoC clk: samsung: Add clock PLL support for ARTPEC-9 SoC dt-bindings: clock: Add ARTPEC-9 clock controller
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml232
-rw-r--r--Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml21
-rw-r--r--drivers/clk/samsung/Makefile1
-rw-r--r--drivers/clk/samsung/clk-artpec9.c1224
-rw-r--r--drivers/clk/samsung/clk-exynos850.c7
-rw-r--r--drivers/clk/samsung/clk-exynosautov920.c52
-rw-r--r--drivers/clk/samsung/clk-gs101.c52
-rw-r--r--drivers/clk/samsung/clk-pll.c185
-rw-r--r--drivers/clk/samsung/clk-pll.h17
-rw-r--r--drivers/clk/samsung/clk.c4
-rw-r--r--include/dt-bindings/clock/axis,artpec9-clk.h195
-rw-r--r--include/dt-bindings/clock/exynos850.h1
-rw-r--r--include/dt-bindings/clock/samsung,exynosautov920.h6
13 files changed, 1960 insertions, 37 deletions
diff --git a/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml b/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml
new file mode 100644
index 000000000000..63442b91e7ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml
@@ -0,0 +1,232 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/axis,artpec9-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axis ARTPEC-9 SoC clock controller
+
+maintainers:
+ - Jesper Nilsson <jesper.nilsson@axis.com>
+
+description: |
+ ARTPEC-9 clock controller is comprised of several CMU (Clock Management Unit)
+ units, generating clocks for different domains. Those CMU units are modeled
+ as separate device tree nodes, and might depend on each other.
+ The root clock in that root tree is an external clock: OSCCLK (25 MHz).
+ This external clock must be defined as a fixed-rate clock in dts.
+
+ CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
+ dividers, all other clocks of function blocks (other CMUs) are usually
+ derived from CMU_CMU.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All clocks available for usage
+ in clock consumer nodes are defined as preprocessor macros in
+ 'include/dt-bindings/clock/axis,artpec9-clk.h' header.
+
+properties:
+ compatible:
+ enum:
+ - axis,artpec9-cmu-cmu
+ - axis,artpec9-cmu-bus
+ - axis,artpec9-cmu-core
+ - axis,artpec9-cmu-cpucl
+ - axis,artpec9-cmu-fsys0
+ - axis,artpec9-cmu-fsys1
+ - axis,artpec9-cmu-imem
+ - axis,artpec9-cmu-peri
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 5
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: axis,artpec9-cmu-cmu
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (25 MHz)
+
+ clock-names:
+ items:
+ - const: fin_pll
+
+ - if:
+ properties:
+ compatible:
+ const: axis,artpec9-cmu-bus
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (25 MHz)
+ - description: CMU_BUS bus clock (from CMU_CMU)
+
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: bus
+
+ - if:
+ properties:
+ compatible:
+ const: axis,artpec9-cmu-core
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (25 MHz)
+ - description: CMU_CORE main clock (from CMU_CMU)
+
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: main
+
+ - if:
+ properties:
+ compatible:
+ const: axis,artpec9-cmu-cpucl
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (25 MHz)
+ - description: CMU_CPUCL switch clock (from CMU_CMU)
+
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: switch
+
+ - if:
+ properties:
+ compatible:
+ const: axis,artpec9-cmu-fsys0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (25 MHz)
+ - description: CMU_FSYS0 bus clock (from CMU_CMU)
+ - description: CMU_FSYS0 IP clock (from CMU_CMU)
+
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: bus
+ - const: ip
+
+ - if:
+ properties:
+ compatible:
+ const: axis,artpec9-cmu-fsys1
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (25 MHz)
+ - description: CMU_FSYS1 scan0 clock (from CMU_CMU)
+ - description: CMU_FSYS1 scan1 clock (from CMU_CMU)
+ - description: CMU_FSYS1 bus clock (from CMU_CMU)
+
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: scan0
+ - const: scan1
+ - const: bus
+
+ - if:
+ properties:
+ compatible:
+ const: axis,artpec9-cmu-imem
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (25 MHz)
+ - description: CMU_IMEM ACLK clock (from CMU_CMU)
+ - description: CMU_IMEM CA5 clock (from CMU_CMU)
+ - description: CMU_IMEM JPEG clock (from CMU_CMU)
+ - description: CMU_IMEM SSS clock (from CMU_CMU)
+
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: aclk
+ - const: ca5
+ - const: jpeg
+ - const: sss
+
+ - if:
+ properties:
+ compatible:
+ const: axis,artpec9-cmu-peri
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (25 MHz)
+ - description: CMU_PERI IP clock (from CMU_CMU)
+ - description: CMU_PERI DISP clock (from CMU_CMU)
+
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: ip
+ - const: disp
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_FSYS1
+ - |
+ #include <dt-bindings/clock/axis,artpec9-clk.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cmu_fsys1: clock-controller@14c10000 {
+ compatible = "axis,artpec9-cmu-fsys1";
+ reg = <0x0 0x14c10000 0x0 0x4000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>,
+ <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>,
+ <&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>;
+ clock-names = "fin_pll", "scan0", "scan1", "bus";
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
index 1318720193b3..6b1fc61a2ff9 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
@@ -35,6 +35,7 @@ properties:
- samsung,exynosautov920-cmu-cpucl0
- samsung,exynosautov920-cmu-cpucl1
- samsung,exynosautov920-cmu-cpucl2
+ - samsung,exynosautov920-cmu-g3d
- samsung,exynosautov920-cmu-hsi0
- samsung,exynosautov920-cmu-hsi1
- samsung,exynosautov920-cmu-hsi2
@@ -287,6 +288,26 @@ allOf:
- const: oscclk
- const: noc
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov920-cmu-g3d
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (38.4 MHz)
+ - description: CMU_G3D SWITCH clock (from CMU_TOP)
+ - description: CMU_G3D NOCP clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: switch
+ - const: nocp
+
required:
- compatible
- "#clock-cells"
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index f3657f2e1b98..b3c4ef4e0dbf 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk-exynos5410.o
obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5420.o
obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5-subcmu.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-artpec8.o
+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-artpec9.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
diff --git a/drivers/clk/samsung/clk-artpec9.c b/drivers/clk/samsung/clk-artpec9.c
new file mode 100644
index 000000000000..2eaf8117638c
--- /dev/null
+++ b/drivers/clk/samsung/clk-artpec9.c
@@ -0,0 +1,1224 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2025 Axis Communications AB.
+ * https://www.axis.com
+ *
+ * Common Clock Framework support for ARTPEC-9 SoC.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/axis,artpec9-clk.h>
+
+#include "clk.h"
+#include "clk-exynos-arm64.h"
+
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CMU_CMU_NR_CLK (CLK_DOUT_CMU_VIO_AUDIO + 1)
+#define CMU_BUS_NR_CLK (CLK_MOUT_BUS_ACLK_USER + 1)
+#define CMU_CORE_NR_CLK (CLK_MOUT_CORE_ACLK_USER + 1)
+#define CMU_CPUCL_NR_CLK (CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG + 1)
+#define CMU_FSYS0_NR_CLK (CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0 + 1)
+#define CMU_FSYS1_NR_CLK (CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK + 1)
+#define CMU_IMEM_NR_CLK (CLK_GOUT_IMEM_PCLK_TMU0_APBIF + 1)
+#define CMU_PERI_NR_CLK (CLK_GOUT_PERI_UART2_SCLK_UART + 1)
+
+/* Register Offset definitions for CMU_CMU (0x12c00000) */
+#define PLL_LOCKTIME_PLL_AUDIO 0x0000
+#define PLL_LOCKTIME_PLL_SHARED0 0x0004
+#define PLL_LOCKTIME_PLL_SHARED1 0x0008
+#define PLL_CON0_PLL_AUDIO 0x0100
+#define PLL_CON0_PLL_SHARED0 0x0120
+#define PLL_CON0_PLL_SHARED1 0x0140
+#define CLK_CON_MUX_CLKCMU_BUS 0x1000
+#define CLK_CON_MUX_CLKCMU_CDC_CORE 0x1004
+#define CLK_CON_MUX_CLKCMU_CORE_MAIN 0x1008
+#define CLK_CON_MUX_CLKCMU_CPUCL_SWITCH 0x100c
+#define CLK_CON_MUX_CLKCMU_VIO_AUDIO 0x1010
+#define CLK_CON_MUX_CLKCMU_DLP_CORE 0x1014
+#define CLK_CON_MUX_CLKCMU_FSYS0_BUS 0x1018
+#define CLK_CON_MUX_CLKCMU_FSYS0_IP 0x101c
+#define CLK_CON_MUX_CLKCMU_FSYS1_BUS 0x1020
+#define CLK_CON_MUX_CLKCMU_FSYS1_SCAN0 0x1024
+#define CLK_CON_MUX_CLKCMU_FSYS1_SCAN1 0x1028
+#define CLK_CON_MUX_CLKCMU_GPU_2D 0x102c
+#define CLK_CON_MUX_CLKCMU_GPU_3D 0x1030
+#define CLK_CON_MUX_CLKCMU_IMEM_ACLK 0x1034
+#define CLK_CON_MUX_CLKCMU_IMEM_CA5 0x1038
+#define CLK_CON_MUX_CLKCMU_IMEM_JPEG 0x103c
+#define CLK_CON_MUX_CLKCMU_IMEM_SSS 0x1040
+#define CLK_CON_MUX_CLKCMU_IPA_CORE 0x1044
+#define CLK_CON_MUX_CLKCMU_MIF_BUSP 0x1048
+#define CLK_CON_MUX_CLKCMU_MIF_SWITCH 0x104c
+#define CLK_CON_MUX_CLKCMU_PERI_DISP 0x1050
+#define CLK_CON_MUX_CLKCMU_PERI_IP 0x1054
+#define CLK_CON_MUX_CLKCMU_RSP_CORE 0x1058
+#define CLK_CON_MUX_CLKCMU_TRFM 0x105c
+#define CLK_CON_MUX_CLKCMU_VIO_CORE 0x1060
+#define CLK_CON_MUX_CLKCMU_VIO_CORE_L 0x1064
+#define CLK_CON_MUX_CLKCMU_VIP0 0x1068
+#define CLK_CON_MUX_CLKCMU_VIP1 0x106c
+#define CLK_CON_MUX_CLKCMU_VPP_CORE 0x1070
+#define CLK_CON_DIV_CLKCMU_ADD 0x1800
+#define CLK_CON_DIV_CLKCMU_BUS 0x1804
+#define CLK_CON_DIV_CLKCMU_CDC_CORE 0x1808
+#define CLK_CON_DIV_CLKCMU_CORE_MAIN 0x180c
+#define CLK_CON_DIV_CLKCMU_CPUCL_SWITCH 0x1810
+#define CLK_CON_DIV_CLKCMU_DLP_CORE 0x1814
+#define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1818
+#define CLK_CON_DIV_CLKCMU_FSYS0_IP 0x181c
+#define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1820
+#define CLK_CON_DIV_CLKCMU_FSYS1_SCAN0 0x1824
+#define CLK_CON_DIV_CLKCMU_FSYS1_SCAN1 0x1828
+#define CLK_CON_DIV_CLKCMU_GPU_2D 0x182c
+#define CLK_CON_DIV_CLKCMU_GPU_3D 0x1830
+#define CLK_CON_DIV_CLKCMU_IMEM_ACLK 0x1834
+#define CLK_CON_DIV_CLKCMU_IMEM_CA5 0x1838
+#define CLK_CON_DIV_CLKCMU_IMEM_JPEG 0x183c
+#define CLK_CON_DIV_CLKCMU_IMEM_SSS 0x1840
+#define CLK_CON_DIV_CLKCMU_IPA_CORE 0x1844
+#define CLK_CON_DIV_CLKCMU_LCPU 0x1848
+#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x184c
+#define CLK_CON_DIV_CLKCMU_MIF_SWITCH 0x1850
+#define CLK_CON_DIV_CLKCMU_PERI_DISP 0x1854
+#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1858
+#define CLK_CON_DIV_CLKCMU_RSP_CORE 0x185c
+#define CLK_CON_DIV_CLKCMU_TRFM 0x1860
+#define CLK_CON_DIV_CLKCMU_VIO_AUDIO 0x1864
+#define CLK_CON_DIV_CLKCMU_VIO_CORE 0x1868
+#define CLK_CON_DIV_CLKCMU_VIO_CORE_L 0x186c
+#define CLK_CON_DIV_CLKCMU_VIP0 0x1870
+#define CLK_CON_DIV_CLKCMU_VIP1 0x1874
+#define CLK_CON_DIV_CLKCMU_VPP_CORE 0x1878
+#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x187c
+#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1880
+#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1884
+#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1888
+#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x188c
+#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1890
+
+static const unsigned long cmu_cmu_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_AUDIO,
+ PLL_LOCKTIME_PLL_SHARED0,
+ PLL_LOCKTIME_PLL_SHARED1,
+ PLL_CON0_PLL_AUDIO,
+ PLL_CON0_PLL_SHARED0,
+ PLL_CON0_PLL_SHARED1,
+ CLK_CON_MUX_CLKCMU_BUS,
+ CLK_CON_MUX_CLKCMU_CDC_CORE,
+ CLK_CON_MUX_CLKCMU_CORE_MAIN,
+ CLK_CON_MUX_CLKCMU_CPUCL_SWITCH,
+ CLK_CON_MUX_CLKCMU_DLP_CORE,
+ CLK_CON_MUX_CLKCMU_FSYS0_BUS,
+ CLK_CON_MUX_CLKCMU_FSYS0_IP,
+ CLK_CON_MUX_CLKCMU_FSYS1_BUS,
+ CLK_CON_MUX_CLKCMU_FSYS1_SCAN0,
+ CLK_CON_MUX_CLKCMU_FSYS1_SCAN1,
+ CLK_CON_MUX_CLKCMU_GPU_2D,
+ CLK_CON_MUX_CLKCMU_GPU_3D,
+ CLK_CON_MUX_CLKCMU_IMEM_ACLK,
+ CLK_CON_MUX_CLKCMU_IMEM_CA5,
+ CLK_CON_MUX_CLKCMU_IMEM_JPEG,
+ CLK_CON_MUX_CLKCMU_IMEM_SSS,
+ CLK_CON_MUX_CLKCMU_IPA_CORE,
+ CLK_CON_MUX_CLKCMU_MIF_BUSP,
+ CLK_CON_MUX_CLKCMU_MIF_SWITCH,
+ CLK_CON_MUX_CLKCMU_PERI_DISP,
+ CLK_CON_MUX_CLKCMU_PERI_IP,
+ CLK_CON_MUX_CLKCMU_RSP_CORE,
+ CLK_CON_MUX_CLKCMU_TRFM,
+ CLK_CON_MUX_CLKCMU_VIO_CORE,
+ CLK_CON_MUX_CLKCMU_VIO_CORE_L,
+ CLK_CON_MUX_CLKCMU_VIP0,
+ CLK_CON_MUX_CLKCMU_VIP1,
+ CLK_CON_MUX_CLKCMU_VPP_CORE,
+ CLK_CON_DIV_CLKCMU_ADD,
+ CLK_CON_DIV_CLKCMU_BUS,
+ CLK_CON_DIV_CLKCMU_CDC_CORE,
+ CLK_CON_DIV_CLKCMU_CORE_MAIN,
+ CLK_CON_DIV_CLKCMU_CPUCL_SWITCH,
+ CLK_CON_DIV_CLKCMU_VIO_AUDIO,
+ CLK_CON_DIV_CLKCMU_DLP_CORE,
+ CLK_CON_DIV_CLKCMU_FSYS0_BUS,
+ CLK_CON_DIV_CLKCMU_FSYS0_IP,
+ CLK_CON_DIV_CLKCMU_FSYS1_BUS,
+ CLK_CON_DIV_CLKCMU_FSYS1_SCAN0,
+ CLK_CON_DIV_CLKCMU_FSYS1_SCAN1,
+ CLK_CON_DIV_CLKCMU_GPU_2D,
+ CLK_CON_DIV_CLKCMU_GPU_3D,
+ CLK_CON_DIV_CLKCMU_IMEM_ACLK,
+ CLK_CON_DIV_CLKCMU_IMEM_CA5,
+ CLK_CON_DIV_CLKCMU_IMEM_JPEG,
+ CLK_CON_DIV_CLKCMU_IMEM_SSS,
+ CLK_CON_DIV_CLKCMU_IPA_CORE,
+ CLK_CON_DIV_CLKCMU_LCPU,
+ CLK_CON_DIV_CLKCMU_MIF_BUSP,
+ CLK_CON_DIV_CLKCMU_MIF_SWITCH,
+ CLK_CON_DIV_CLKCMU_PERI_DISP,
+ CLK_CON_DIV_CLKCMU_PERI_IP,
+ CLK_CON_DIV_CLKCMU_RSP_CORE,
+ CLK_CON_DIV_CLKCMU_TRFM,
+ CLK_CON_DIV_CLKCMU_VIO_AUDIO,
+ CLK_CON_DIV_CLKCMU_VIO_CORE,
+ CLK_CON_DIV_CLKCMU_VIO_CORE_L,
+ CLK_CON_DIV_CLKCMU_VIP0,
+ CLK_CON_DIV_CLKCMU_VIP1,
+ CLK_CON_DIV_CLKCMU_VPP_CORE,
+ CLK_CON_DIV_PLL_SHARED0_DIV2,
+ CLK_CON_DIV_PLL_SHARED0_DIV3,
+ CLK_CON_DIV_PLL_SHARED0_DIV4,
+ CLK_CON_DIV_PLL_SHARED1_DIV2,
+ CLK_CON_DIV_PLL_SHARED1_DIV3,
+ CLK_CON_DIV_PLL_SHARED1_DIV4,
+};
+
+static const struct samsung_pll_rate_table artpec9_pll_audio_rates[] __initconst = {
+ PLL_A9FRACO_RATE(25 * MHZ, 589824000U, 94, 1, 3, 6238440),
+};
+
+static const struct samsung_pll_clock cmu_cmu_pll_clks[] __initconst = {
+ PLL(pll_a9fracm, CLK_FOUT_SHARED0_PLL, "fout_pll_shared0", "fin_pll",
+ PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, NULL),
+ PLL(pll_a9fracm, CLK_FOUT_SHARED1_PLL, "fout_pll_shared1", "fin_pll",
+ PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, NULL),
+ PLL(pll_a9fraco, CLK_FOUT_AUDIO_PLL, "fout_pll_audio", "fin_pll",
+ PLL_LOCKTIME_PLL_AUDIO, PLL_CON0_PLL_AUDIO, artpec9_pll_audio_rates),
+};
+
+PNAME(mout_clkcmu_bus_bus_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
+ "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_cdc_core_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div3",
+ "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
+PNAME(mout_clkcmu_core_main_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
+ "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_cpucl_switch_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
+ "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_dlp_core_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
+PNAME(mout_clkcmu_fsys0_bus_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div4", "dout_pll_shared1_div2" };
+PNAME(mout_clkcmu_fsys0_ip_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div3",
+ "dout_pll_shared1_div2", "dout_pll_shared0_div3" };
+PNAME(mout_clkcmu_fsys1_bus_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div2", "dout_pll_shared0_div4" };
+PNAME(mout_clkcmu_fsys1_scan0_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_fsys1_scan1_p) = { "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_gpu_3d_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
+PNAME(mout_clkcmu_gpu_2d_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
+PNAME(mout_clkcmu_imem_aclk_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div4", "dout_pll_shared1_div2" };
+PNAME(mout_clkcmu_imem_ca5_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
+ "dout_pll_shared1_div3", "mout_clk_pll_shared1" };
+PNAME(mout_clkcmu_imem_jpeg_p) = { "dout_pll_shared0_div2", "dout_pll_shared0_div3",
+ "dout_pll_shared1_div2", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_imem_sss_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2" };
+PNAME(mout_clkcmu_ipa_core_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
+PNAME(mout_clkcmu_mif_switch_p) = { "fout_pll_shared1", "mout_clkcmu_pll_shared0",
+ "dout_pll_shared0_div2", "dout_pll_shared0_div3" };
+PNAME(mout_clkcmu_mif_busp_p) = { "dout_pll_shared1_div3", "dout_pll_shared1_div4",
+ "dout_pll_shared0_div4", "dout_pll_shared0_div2" };
+PNAME(mout_clkcmu_peri_disp_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div4", "dout_pll_shared1_div2" };
+PNAME(mout_clkcmu_peri_ip_p) = { "fout_pll_fsys1", "dout_pll_shared1_2",
+ "dout_pll_shared1_div4", "dout_pll_shared0_div2" };
+PNAME(mout_clkcmu_rsp_core_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
+PNAME(mout_clkcmu_trfm_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
+PNAME(mout_clkcmu_vio_core_l_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div3",
+ "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
+PNAME(mout_clkcmu_vio_core_p) = { "fout_pll_fsys1", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div3", "dout_pll_shared1_div2" };
+PNAME(mout_clkcmu_vio_audio_p) = { "fout_pll_audio", "mout_clkcmu_pll_audio" };
+PNAME(mout_clkcmu_vip0_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
+PNAME(mout_clkcmu_vip1_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
+PNAME(mout_clkcmu_vpp_core_p) = { "dout_pll_shared1_div3", "dout_pll_shared0_div2",
+ "dout_pll_shared1_div2", "mout_clk_pll_fsys1" };
+PNAME(mout_clkcmu_pll_shared0_p) = { "fin_pll", "fout_pll_shared0" };
+PNAME(mout_clkcmu_pll_shared1_p) = { "fin_pll", "fout_pll_shared1" };
+PNAME(mout_clkcmu_pll_audio_p) = { "fin_pll", "fout_pll_audio" };
+
+static const struct samsung_mux_clock cmu_cmu_mux_clks[] __initconst = {
+ MUX(0, "mout_clkcmu_pll_shared0", mout_clkcmu_pll_shared0_p, PLL_CON0_PLL_SHARED0, 4, 1),
+ MUX(0, "mout_clkcmu_pll_shared1", mout_clkcmu_pll_shared1_p, PLL_CON0_PLL_SHARED1, 4, 1),
+ MUX(0, "mout_clkcmu_pll_audio", mout_clkcmu_pll_audio_p, PLL_CON0_PLL_AUDIO, 4, 1),
+ MUX(0, "mout_clkcmu_bus_bus", mout_clkcmu_bus_bus_p, CLK_CON_MUX_CLKCMU_BUS, 0, 2),
+ nMUX(0, "mout_clkcmu_cdc_core", mout_clkcmu_cdc_core_p, CLK_CON_MUX_CLKCMU_CDC_CORE, 0, 2),
+ MUX(0, "mout_clkcmu_core_main", mout_clkcmu_core_main_p,
+ CLK_CON_MUX_CLKCMU_CORE_MAIN, 0, 2),
+ MUX(0, "mout_clkcmu_cpucl_switch", mout_clkcmu_cpucl_switch_p,
+ CLK_CON_MUX_CLKCMU_CPUCL_SWITCH, 0, 2),
+ nMUX(0, "mout_clkcmu_dlp_core", mout_clkcmu_dlp_core_p, CLK_CON_MUX_CLKCMU_DLP_CORE, 0, 2),
+ MUX(0, "mout_clkcmu_fsys0_bus", mout_clkcmu_fsys0_bus_p,
+ CLK_CON_MUX_CLKCMU_FSYS0_BUS, 0, 2),
+ MUX(0, "mout_clkcmu_fsys0_ip", mout_clkcmu_fsys0_ip_p, CLK_CON_MUX_CLKCMU_FSYS0_IP, 0, 2),
+ MUX(0, "mout_clkcmu_fsys1_bus", mout_clkcmu_fsys1_bus_p,
+ CLK_CON_MUX_CLKCMU_FSYS1_BUS, 0, 2),
+ MUX(0, "mout_clkcmu_fsys1_scan0", mout_clkcmu_fsys1_scan0_p,
+ CLK_CON_MUX_CLKCMU_FSYS1_SCAN0, 0, 1),
+ MUX(0, "mout_clkcmu_fsys1_scan1", mout_clkcmu_fsys1_scan1_p,
+ CLK_CON_MUX_CLKCMU_FSYS1_SCAN1, 0, 1),
+ MUX(0, "mout_clkcmu_gpu_2d", mout_clkcmu_gpu_2d_p, CLK_CON_MUX_CLKCMU_GPU_2D, 0, 2),
+ MUX(0, "mout_clkcmu_gpu_3d", mout_clkcmu_gpu_3d_p, CLK_CON_MUX_CLKCMU_GPU_3D, 0, 2),
+ MUX(0, "mout_clkcmu_imem_aclk", mout_clkcmu_imem_aclk_p,
+ CLK_CON_MUX_CLKCMU_IMEM_ACLK, 0, 2),
+ MUX(0, "mout_clkcmu_imem_ca5", mout_clkcmu_imem_ca5_p, CLK_CON_MUX_CLKCMU_IMEM_CA5, 0, 2),
+ MUX(0, "mout_clkcmu_imem_jpeg", mout_clkcmu_imem_jpeg_p,
+ CLK_CON_MUX_CLKCMU_IMEM_JPEG, 0, 2),
+ MUX(0, "mout_clkcmu_imem_sss", mout_clkcmu_imem_sss_p, CLK_CON_MUX_CLKCMU_IMEM_SSS, 0, 1),
+ MUX(0, "mout_clkcmu_ipa_core", mout_clkcmu_ipa_core_p, CLK_CON_MUX_CLKCMU_IPA_CORE, 0, 2),
+ MUX(0, "mout_clkcmu_mif_busp", mout_clkcmu_mif_busp_p, CLK_CON_MUX_CLKCMU_MIF_BUSP, 0, 2),
+ MUX(0, "mout_clkcmu_mif_switch", mout_clkcmu_mif_switch_p,
+ CLK_CON_MUX_CLKCMU_MIF_SWITCH, 0, 2),
+ MUX(0, "mout_clkcmu_peri_disp", mout_clkcmu_peri_disp_p,
+ CLK_CON_MUX_CLKCMU_PERI_DISP, 0, 2),
+ MUX(0, "mout_clkcmu_peri_ip", mout_clkcmu_peri_ip_p, CLK_CON_MUX_CLKCMU_PERI_IP, 0, 2),
+ MUX(0, "mout_clkcmu_rsp_core", mout_clkcmu_rsp_core_p, CLK_CON_MUX_CLKCMU_RSP_CORE, 0, 2),
+ MUX(0, "mout_clkcmu_trfm", mout_clkcmu_trfm_p, CLK_CON_MUX_CLKCMU_TRFM, 0, 2),
+ MUX(0, "mout_clkcmu_vio_core", mout_clkcmu_vio_core_p, CLK_CON_MUX_CLKCMU_VIO_CORE, 0, 2),
+ MUX(0, "mout_clkcmu_vio_core_l", mout_clkcmu_vio_core_l_p,
+ CLK_CON_MUX_CLKCMU_VIO_CORE_L, 0, 2),
+ MUX(0, "mout_clkcmu_vio_audio", mout_clkcmu_vio_audio_p,
+ CLK_CON_MUX_CLKCMU_VIO_AUDIO, 0, 1),
+ MUX(0, "mout_clkcmu_vip0", mout_clkcmu_vip0_p, CLK_CON_MUX_CLKCMU_VIP0, 0, 2),
+ MUX(0, "mout_clkcmu_vip1", mout_clkcmu_vip1_p, CLK_CON_MUX_CLKCMU_VIP1, 0, 2),
+ MUX(0, "mout_clkcmu_vpp_core", mout_clkcmu_vpp_core_p, CLK_CON_MUX_CLKCMU_VPP_CORE, 0, 2),
+};
+
+static const struct samsung_div_clock cmu_cmu_div_clks[] __initconst = {
+ DIV(CLK_DOUT_CMU_ADD, "dout_clkcmu_add", "gate_clkcmu_add", CLK_CON_DIV_CLKCMU_ADD, 0, 8),
+ DIV(CLK_DOUT_CMU_BUS, "dout_clkcmu_bus",
+ "gate_clkcmu_bus_bus", CLK_CON_DIV_CLKCMU_BUS, 0, 4),
+ DIV_F(CLK_DOUT_CMU_CDC_CORE, "dout_clkcmu_cdc_core",
+ "gate_clkcmu_cdc_core", CLK_CON_DIV_CLKCMU_CDC_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DOUT_CMU_CORE_MAIN, "dout_clkcmu_core_main",
+ "gate_clkcmu_core_main", CLK_CON_DIV_CLKCMU_CORE_MAIN, 0, 4),
+ DIV(CLK_DOUT_CMU_CPUCL_SWITCH, "dout_clkcmu_cpucl_switch",
+ "gate_clkcmu_cpucl_switch", CLK_CON_DIV_CLKCMU_CPUCL_SWITCH, 0, 3),
+ DIV_F(CLK_DOUT_CMU_DLP_CORE, "dout_clkcmu_dlp_core",
+ "gate_clkcmu_dlp_core", CLK_CON_DIV_CLKCMU_DLP_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DOUT_CMU_FSYS0_BUS, "dout_clkcmu_fsys0_bus",
+ "gate_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
+ DIV(CLK_DOUT_CMU_FSYS0_IP, "dout_clkcmu_fsys0_ip",
+ "gate_clkcmu_fsys0_ip", CLK_CON_DIV_CLKCMU_FSYS0_IP, 0, 9),
+ DIV(CLK_DOUT_CMU_FSYS1_BUS, "dout_clkcmu_fsys1_bus",
+ "gate_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
+ DIV(CLK_DOUT_CMU_FSYS1_SCAN0, "dout_clkcmu_fsys1_scan0",
+ "gate_clkcmu_fsys1_scan0", CLK_CON_DIV_CLKCMU_FSYS1_SCAN0, 0, 4),
+ DIV(CLK_DOUT_CMU_FSYS1_SCAN1, "dout_clkcmu_fsys1_scan1",
+ "gate_clkcmu_fsys1_scan1", CLK_CON_DIV_CLKCMU_FSYS1_SCAN1, 0, 4),
+ DIV(CLK_DOUT_CMU_GPU_2D, "dout_clkcmu_gpu_2d",
+ "gate_clkcmu_gpu_2d", CLK_CON_DIV_CLKCMU_GPU_2D, 0, 4),
+ DIV(CLK_DOUT_CMU_GPU_3D, "dout_clkcmu_gpu_3d",
+ "gate_clkcmu_gpu_3d", CLK_CON_DIV_CLKCMU_GPU_3D, 0, 4),
+ DIV(CLK_DOUT_CMU_IMEM_ACLK, "dout_clkcmu_imem_aclk",
+ "gate_clkcmu_imem_aclk", CLK_CON_DIV_CLKCMU_IMEM_ACLK, 0, 4),
+ DIV(CLK_DOUT_CMU_IMEM_CA5, "dout_clkcmu_imem_ca5",
+ "gate_clkcmu_imem_ca5", CLK_CON_DIV_CLKCMU_IMEM_CA5, 0, 4),
+ DIV(CLK_DOUT_CMU_IMEM_JPEG, "dout_clkcmu_imem_jpeg",
+ "gate_clkcmu_imem_jpeg", CLK_CON_DIV_CLKCMU_IMEM_JPEG, 0, 4),
+ DIV(CLK_DOUT_CMU_IMEM_SSS, "dout_clkcmu_imem_sss",
+ "gate_clkcmu_imem_sss", CLK_CON_DIV_CLKCMU_IMEM_SSS, 0, 4),
+ DIV(CLK_DOUT_CMU_IPA_CORE, "dout_clkcmu_ipa_core",
+ "gate_clkcmu_ipa_core", CLK_CON_DIV_CLKCMU_IPA_CORE, 0, 4),
+ DIV(CLK_DOUT_CMU_LCPU, "dout_clkcmu_lcpu",
+ "gate_clkcmu_lcpu", CLK_CON_DIV_CLKCMU_LCPU, 0, 4),
+ DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_clkcmu_mif_busp",
+ "gate_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 3),
+ DIV(CLK_DOUT_CMU_MIF_SWITCH, "dout_clkcmu_mif_switch",
+ "gate_clkcmu_mif_switch", CLK_CON_DIV_CLKCMU_MIF_SWITCH, 0, 4),
+ DIV(CLK_DOUT_CMU_PERI_DISP, "dout_clkcmu_peri_disp",
+ "gate_clkcmu_peri_disp", CLK_CON_DIV_CLKCMU_PERI_DISP, 0, 4),
+ DIV(CLK_DOUT_CMU_PERI_IP, "dout_clkcmu_peri_ip",
+ "gate_clkcmu_peri_ip", CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
+ DIV(CLK_DOUT_CMU_RSP_CORE, "dout_clkcmu_rsp_core",
+ "gate_clkcmu_rsp_core", CLK_CON_DIV_CLKCMU_RSP_CORE, 0, 4),
+ DIV(CLK_DOUT_CMU_TRFM, "dout_clkcmu_trfm",
+ "gate_clkcmu_trfm", CLK_CON_DIV_CLKCMU_TRFM, 0, 4),
+ DIV(CLK_DOUT_CMU_VIO_CORE, "dout_clkcmu_vio_core",
+ "gate_clkcmu_vio_core", CLK_CON_DIV_CLKCMU_VIO_CORE, 0, 4),
+ DIV(CLK_DOUT_CMU_VIO_CORE_L, "dout_clkcmu_vio_core_l",
+ "gate_clkcmu_vio_core_l", CLK_CON_DIV_CLKCMU_VIO_CORE_L, 0, 4),
+ DIV(CLK_DOUT_CMU_VIO_AUDIO, "dout_clkcmu_vio_audio",
+ "gate_clkcmu_vio_audio", CLK_CON_DIV_CLKCMU_VIO_AUDIO, 0, 4),
+ DIV(CLK_DOUT_CMU_VIP0, "dout_clkcmu_vip0",
+ "gate_clkcmu_vip0", CLK_CON_DIV_CLKCMU_VIP0, 0, 4),
+ DIV(CLK_DOUT_CMU_VIP1, "dout_clkcmu_vip1",
+ "gate_clkcmu_vip1", CLK_CON_DIV_CLKCMU_VIP1, 0, 4),
+ DIV(CLK_DOUT_CMU_VPP_CORE, "dout_clkcmu_vpp_core",
+ "gate_clkcmu_vpp_core", CLK_CON_DIV_CLKCMU_VPP_CORE, 0, 4),
+ DIV(CLK_DOUT_SHARED0_DIV2, "dout_pll_shared0_div2",
+ "mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
+ DIV(CLK_DOUT_SHARED0_DIV3, "dout_pll_shared0_div3",
+ "mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
+ DIV(CLK_DOUT_SHARED0_DIV4, "dout_pll_shared0_div4",
+ "dout_pll_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
+ DIV(CLK_DOUT_SHARED1_DIV2, "dout_pll_shared1_div2",
+ "mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
+ DIV(CLK_DOUT_SHARED1_DIV3, "dout_pll_shared1_div3",
+ "mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
+ DIV(CLK_DOUT_SHARED1_DIV4, "dout_pll_shared1_div4",
+ "dout_pll_shared1_div2", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
+};
+
+static const struct samsung_cmu_info cmu_cmu_info __initconst = {
+ .pll_clks = cmu_cmu_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cmu_cmu_pll_clks),
+ .mux_clks = cmu_cmu_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_cmu_mux_clks),
+ .div_clks = cmu_cmu_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cmu_cmu_div_clks),
+ .nr_clk_ids = CMU_CMU_NR_CLK,
+ .clk_regs = cmu_cmu_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_cmu_clk_regs),
+};
+
+/* Register Offset definitions for CMU_BUS (0x13410000) */
+#define PLL_CON0_MUX_CLK_BUS_ACLK_USER 0x0100
+
+static const unsigned long cmu_bus_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLK_BUS_ACLK_USER,
+};
+
+PNAME(mout_clk_bus_aclk_user_p) = {"fin_pll", "dout_clkcmu_bus_bus",};
+
+static const struct samsung_mux_clock cmu_bus_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_BUS_ACLK_USER, "mout_clk_bus_aclk_user", mout_clk_bus_aclk_user_p,
+ PLL_CON0_MUX_CLK_BUS_ACLK_USER, 4, 1),
+};
+
+static const struct samsung_cmu_info cmu_bus_info __initconst = {
+ .mux_clks = cmu_bus_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_bus_mux_clks),
+ .nr_clk_ids = CMU_BUS_NR_CLK,
+ .clk_regs = cmu_bus_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_bus_clk_regs),
+};
+
+/* Register Offset definitions for CMU_CORE (0x12c10000) */
+#define PLL_CON0_MUX_CLK_CORE_ACLK_USER 0x0100
+
+static const unsigned long cmu_core_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLK_CORE_ACLK_USER,
+};
+
+PNAME(mout_clk_core_aclk_user_p) = {"fin_pll", "dout_clkcmu_core_main",};
+
+static const struct samsung_mux_clock cmu_core_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_CORE_ACLK_USER, "mout_clk_core_aclk_user", mout_clk_core_aclk_user_p,
+ PLL_CON0_MUX_CLK_CORE_ACLK_USER, 4, 1),
+};
+
+static const struct samsung_cmu_info cmu_core_info __initconst = {
+ .mux_clks = cmu_core_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_core_mux_clks),
+ .nr_clk_ids = CMU_CORE_NR_CLK,
+ .clk_regs = cmu_core_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_core_clk_regs),
+};
+
+/* Register Offset definitions for CMU_CPUCL (0x12810000) */
+#define PLL_LOCKTIME_PLL0_CPUCL 0x0000
+#define PLL_LOCKTIME_PLL1_CPUCL 0x0008
+#define PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_SCU_USER 0x0100
+#define PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER 0x0120
+#define PLL_CON0_PLL0_CPUCL 0x0140
+#define PLL_CON0_PLL1_CPUCL 0x0160
+#define CLK_CON_MUX_CLK_CPUCL_PLL 0x1000
+#define CLK_CON_MUX_CLK_CPUCL_PLL_SCU 0x1004
+#define CLK_CON_DIV_CLK_CPUCL_CLUSTER_PERIPHCLK 0x1800
+#define CLK_CON_DIV_CLK_CPUCL_CLUSTER_GICCLK 0x1804
+#define CLK_CON_DIV_CLK_CPUCL_CLUSTER_PCLK 0x1808
+#define CLK_CON_DIV_CLK_CPUCL_CMUREF 0x180c
+#define CLK_CON_DIV_CLK_CPUCL_CPU 0x1810
+#define CLK_CON_DIV_CLK_CPUCL_CLUSTER_ATCLK 0x1818
+#define CLK_CON_DIV_CLK_CPUCL_CLUSTER_SCU 0x181c
+#define CLK_CON_DIV_CLK_CPUCL_DBG 0x1820
+#define CLK_CON_GAT_CLK_CLUSTER_CPU 0x2008
+#define CLK_CON_GAT_CLK_CPUCL_SHORTSTOP 0x200c
+#define CSSYS_IPCLKPORT_ATCLK 0x2070
+#define CSSYS_IPCLKPORT_PCLKDBG 0x2074
+#define DMYQCH_CON_CSSYS_QCH 0x3000
+#define DMYQCH_CON_CLUSTER_QCH_CORECLK0 0x3104
+#define DMYQCH_CON_CLUSTER_QCH_CORECLK1 0x3108
+#define DMYQCH_CON_CLUSTER_QCH_CORECLK2 0x310c
+#define DMYQCH_CON_CLUSTER_QCH_CORECLK3 0x3110
+#define DMYQCH_CON_CLUSTER_QCH_CORECLK4 0x3114
+#define DMYQCH_CON_CLUSTER_QCH_CORECLK5 0x3118
+#define DMYQCH_CON_CLUSTER_QCH_PERIPHCLK 0x311c
+
+static const unsigned long cmu_cpucl_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL0_CPUCL,
+ PLL_LOCKTIME_PLL1_CPUCL,
+ PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_SCU_USER,
+ PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER,
+ PLL_CON0_PLL0_CPUCL,
+ PLL_CON0_PLL1_CPUCL,
+ CLK_CON_MUX_CLK_CPUCL_PLL,
+ CLK_CON_MUX_CLK_CPUCL_PLL_SCU,
+ CLK_CON_DIV_CLK_CPUCL_CLUSTER_PERIPHCLK,
+ CLK_CON_DIV_CLK_CPUCL_CLUSTER_GICCLK,
+ CLK_CON_DIV_CLK_CPUCL_CLUSTER_PCLK,
+ CLK_CON_DIV_CLK_CPUCL_CMUREF,
+ CLK_CON_DIV_CLK_CPUCL_CPU,
+ CLK_CON_DIV_CLK_CPUCL_CLUSTER_ATCLK,
+ CLK_CON_DIV_CLK_CPUCL_CLUSTER_SCU,
+ CLK_CON_DIV_CLK_CPUCL_DBG,
+ CLK_CON_GAT_CLK_CLUSTER_CPU,
+ CLK_CON_GAT_CLK_CPUCL_SHORTSTOP,
+ CSSYS_IPCLKPORT_ATCLK,
+ CSSYS_IPCLKPORT_PCLKDBG,
+ DMYQCH_CON_CSSYS_QCH,
+ DMYQCH_CON_CLUSTER_QCH_CORECLK0,
+ DMYQCH_CON_CLUSTER_QCH_CORECLK1,
+ DMYQCH_CON_CLUSTER_QCH_CORECLK2,
+ DMYQCH_CON_CLUSTER_QCH_CORECLK3,
+ DMYQCH_CON_CLUSTER_QCH_CORECLK4,
+ DMYQCH_CON_CLUSTER_QCH_CORECLK5,
+ DMYQCH_CON_CLUSTER_QCH_PERIPHCLK,
+};
+
+/* rate_table must be in descending order */
+static const struct samsung_pll_rate_table artpec9_pll_cpucl_rates[] __initconst = {
+ PLL_35XX_RATE(25 * MHZ, 1400000000U, 56, 1, 0),
+ PLL_35XX_RATE(25 * MHZ, 1100000000U, 44, 1, 0),
+ PLL_35XX_RATE(25 * MHZ, 850000000U, 34, 1, 0),
+};
+
+static const struct samsung_pll_clock cmu_cpucl_pll_clks[] __initconst = {
+ PLL(pll_a9fracm, CLK_FOUT_CPUCL_PLL0, "fout_pll0_cpucl", "fin_pll",
+ PLL_LOCKTIME_PLL0_CPUCL, PLL_CON0_PLL0_CPUCL, artpec9_pll_cpucl_rates),
+ PLL(pll_a9fracm, CLK_FOUT_CPUCL_PLL1, "fout_pll1_cpucl", "fin_pll",
+ PLL_LOCKTIME_PLL1_CPUCL, PLL_CON0_PLL1_CPUCL, artpec9_pll_cpucl_rates),
+};
+
+PNAME(mout_clkcmu_cpucl_switch_scu_user_p) = { "fin_pll", "dout_clkcmu_cpucl_switch" };
+PNAME(mout_clkcmu_cpucl_switch_user_p) = { "fin_pll", "dout_clkcmu_cpucl_switch" };
+PNAME(mout_pll0_cpucl_p) = { "fin_pll", "fout_pll0_cpucl" };
+PNAME(mout_clk_cpucl_pll0_p) = { "mout_pll0_cpucl", "mout_clkcmu_cpucl_switch_user" };
+PNAME(mout_pll1_cpucl_p) = { "fin_pll", "fout_pll1_cpucl" };
+PNAME(mout_clk_cpucl_pll_scu_p) = { "mout_pll1_cpucl", "mout_clkcmu_cpucl_switch_scu_user" };
+
+static const struct samsung_mux_clock cmu_cpucl_mux_clks[] __initconst = {
+ MUX_F(0, "mout_pll0_cpucl", mout_pll0_cpucl_p,
+ PLL_CON0_PLL0_CPUCL, 4, 1, CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
+ MUX_F(0, "mout_pll1_cpucl", mout_pll1_cpucl_p,
+ PLL_CON0_PLL1_CPUCL, 4, 1, CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
+ MUX(CLK_MOUT_CPUCL_SWITCH_SCU_USER, "mout_clkcmu_cpucl_switch_scu_user",
+ mout_clkcmu_cpucl_switch_scu_user_p, PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_SCU_USER, 4, 1),
+ MUX(CLK_MOUT_CPUCL_SWITCH_USER, "mout_clkcmu_cpucl_switch_user",
+ mout_clkcmu_cpucl_switch_user_p, PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER, 4, 1),
+ MUX_F(CLK_MOUT_CPUCL_PLL0, "mout_clk_cpucl_pll0",
+ mout_clk_cpucl_pll0_p, CLK_CON_MUX_CLK_CPUCL_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
+ MUX_F(CLK_MOUT_CPUCL_PLL_SCU, "mout_clk_cpucl_pll_scu", mout_clk_cpucl_pll_scu_p,
+ CLK_CON_MUX_CLK_CPUCL_PLL_SCU, 0, 1, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_fixed_factor_clock cpucl_ffactor_clks[] __initconst = {
+ FFACTOR(CLK_DOUT_CPUCL_CPU, "dout_clk_cpucl_cpu",
+ "mout_clk_cpucl_pll0", 1, 1, CLK_SET_RATE_PARENT),
+};
+
+static const struct samsung_div_clock cmu_cpucl_div_clks[] __initconst = {
+ DIV(CLK_DOUT_CPUCL_CLUSTER_PERIPHCLK, "dout_clk_cluster_periphclk",
+ "clk_con_gat_clk_cluster_cpu", CLK_CON_DIV_CLK_CPUCL_CLUSTER_PERIPHCLK, 0, 4),
+ DIV(CLK_DOUT_CPUCL_CLUSTER_GICCLK, "dout_clk_cluster_gicclk",
+ "clk_con_gat_clk_cluster_cpu", CLK_CON_DIV_CLK_CPUCL_CLUSTER_GICCLK, 0, 4),
+ DIV(CLK_DOUT_CPUCL_CLUSTER_PCLK, "dout_clk_cluster_pclk",
+ "clk_con_gat_clk_cluster_cpu", CLK_CON_DIV_CLK_CPUCL_CLUSTER_PCLK, 0, 4),
+ DIV(CLK_DOUT_CPUCL_CMUREF, "dout_clk_cpucl_cmuref",
+ "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_CMUREF, 0, 3),
+ DIV(CLK_DOUT_CPUCL_CLUSTER_ATCLK, "dout_clk_cluster_atclk",
+ "clk_con_gat_clk_cluster_cpu", CLK_CON_DIV_CLK_CPUCL_CLUSTER_ATCLK, 0, 4),
+ DIV_F(CLK_DOUT_CPUCL_CLUSTER_SCU, "dout_clk_cluster_scu", "mout_clk_cpucl_pll_scu",
+ CLK_CON_DIV_CLK_CPUCL_CLUSTER_SCU, 0, 4, CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DOUT_CPUCL_DBG, "dout_clk_cpucl_dbg",
+ "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_DBG, 0, 4),
+};
+
+static const struct samsung_gate_clock cmu_cpucl_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_CPUCL_CLUSTER_CPU, "clk_con_gat_clk_cluster_cpu",
+ "clk_con_gat_clk_cpucl_shortstop", CLK_CON_GAT_CLK_CLUSTER_CPU, 21,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_CPUCL_SHORTSTOP, "clk_con_gat_clk_cpucl_shortstop", "dout_clk_cpucl_cpu",
+ CLK_CON_GAT_CLK_CPUCL_SHORTSTOP, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK, "cssys_ipclkport_atclk", "dout_clk_cpucl_dbg",
+ CSSYS_IPCLKPORT_ATCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG, "cssys_ipclkport_pclkdbg",
+ "dout_clk_cpucl_dbg", CSSYS_IPCLKPORT_PCLKDBG, 21,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info cmu_cpucl_info __initconst = {
+ .pll_clks = cmu_cpucl_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cmu_cpucl_pll_clks),
+ .fixed_factor_clks = cpucl_ffactor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(cpucl_ffactor_clks),
+ .mux_clks = cmu_cpucl_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_cpucl_mux_clks),
+ .div_clks = cmu_cpucl_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cmu_cpucl_div_clks),
+ .gate_clks = cmu_cpucl_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cmu_cpucl_gate_clks),
+ .nr_clk_ids = CMU_CPUCL_NR_CLK,
+ .clk_regs = cmu_cpucl_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_cpucl_clk_regs),
+};
+
+/* Register Offset definitions for CMU_FSYS0 (0x14410000) */
+#define PLL_CON0_MUX_CLK_FSYS0_BUS_USER 0x0100
+#define PLL_CON0_MUX_CLK_FSYS0_IP_USER 0x0120
+#define PLL_CON0_MUX_CLK_FSYS0_MAIN_USER 0x0140
+#define CLK_CON_DIV_CLK_FSYS0_125 0x1800
+#define CLK_CON_DIV_CLK_FSYS0_ADC 0x1804
+#define CLK_CON_DIV_CLK_FSYS0_BUS_300 0x1808
+#define CLK_CON_DIV_CLK_FSYS0_EQOS0 0x1814
+#define CLK_CON_DIV_CLK_FSYS0_EQOS1 0x1818
+#define CLK_CON_DIV_CLK_FSYS0_EQOS_250 0x181C
+#define CLK_CON_DIV_CLK_FSYS0_MMC_CARD0 0x1820
+#define CLK_CON_DIV_CLK_FSYS0_MMC_CARD1 0x1824
+#define CLK_CON_DIV_CLK_FSYS0_MMC_CARD2 0x1828
+#define CLK_CON_DIV_CLK_FSYS0_QSPI 0x182c
+#define CLK_CON_DIV_CLK_FSYS0_SFMC_NAND 0x1830
+#define CLK_CON_FSYS0_I2C0_IPCLKPORT_I_PCLK 0x2040
+#define CLK_CON_FSYS0_I2C1_IPCLKPORT_I_PCLK 0x2044
+#define CLK_CON_MMC0_IPCLKPORT_I_ACLK 0x2078
+#define CLK_CON_MMC1_IPCLKPORT_I_ACLK 0x2080
+#define CLK_CON_MMC2_IPCLKPORT_I_ACLK 0x2088
+#define CLK_CON_PWM_IPCLKPORT_I_PCLK_S0 0x2090
+#define CLK_CON_DMYQCH_CON_ADC_WRAP_QCH 0x3000
+#define CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH 0x3004
+#define CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH 0x3008
+#define CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH 0x3010
+#define CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH 0x3014
+#define CLK_CON_DMYQCH_CON_MMC0_QCH 0x3018
+#define CLK_CON_DMYQCH_CON_MMC1_QCH 0x301c
+#define CLK_CON_DMYQCH_CON_MMC2_QCH 0x3020
+#define CLK_CON_DMYQCH_CON_QSPI_QCH 0x3024
+#define CLK_CON_DMYQCH_CON_SFMC_QCH 0x3028
+
+static const unsigned long cmu_fsys0_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLK_FSYS0_BUS_USER,
+ PLL_CON0_MUX_CLK_FSYS0_IP_USER,
+ PLL_CON0_MUX_CLK_FSYS0_MAIN_USER,
+ CLK_CON_DIV_CLK_FSYS0_125,
+ CLK_CON_DIV_CLK_FSYS0_ADC,
+ CLK_CON_DIV_CLK_FSYS0_BUS_300,
+ CLK_CON_DIV_CLK_FSYS0_EQOS0,
+ CLK_CON_DIV_CLK_FSYS0_EQOS1,
+ CLK_CON_DIV_CLK_FSYS0_EQOS_250,
+ CLK_CON_DIV_CLK_FSYS0_MMC_CARD0,
+ CLK_CON_DIV_CLK_FSYS0_MMC_CARD1,
+ CLK_CON_DIV_CLK_FSYS0_MMC_CARD2,
+ CLK_CON_DIV_CLK_FSYS0_QSPI,
+ CLK_CON_DIV_CLK_FSYS0_SFMC_NAND,
+ CLK_CON_FSYS0_I2C0_IPCLKPORT_I_PCLK,
+ CLK_CON_FSYS0_I2C1_IPCLKPORT_I_PCLK,
+ CLK_CON_MMC0_IPCLKPORT_I_ACLK,
+ CLK_CON_MMC1_IPCLKPORT_I_ACLK,
+ CLK_CON_MMC2_IPCLKPORT_I_ACLK,
+ CLK_CON_PWM_IPCLKPORT_I_PCLK_S0,
+ CLK_CON_DMYQCH_CON_ADC_WRAP_QCH,
+ CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH,
+ CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH,
+ CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH,
+ CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH,
+ CLK_CON_DMYQCH_CON_MMC0_QCH,
+ CLK_CON_DMYQCH_CON_MMC1_QCH,
+ CLK_CON_DMYQCH_CON_MMC2_QCH,
+ CLK_CON_DMYQCH_CON_QSPI_QCH,
+ CLK_CON_DMYQCH_CON_SFMC_QCH,
+};
+
+PNAME(mout_fsys0_bus_user_p) = { "fin_pll", "dout_clkcmu_fsys0_bus" };
+PNAME(mout_fsys0_ip_user_p) = { "fin_pll", "dout_clkcmu_fsys0_ip" };
+PNAME(mout_fsys0_main_user_p) = { "fin_pll", "fout_pll_fsys1" };
+
+static const struct samsung_mux_clock cmu_fsys0_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user",
+ mout_fsys0_bus_user_p, PLL_CON0_MUX_CLK_FSYS0_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_FSYS0_IP_USER, "mout_fsys0_ip_user",
+ mout_fsys0_ip_user_p, PLL_CON0_MUX_CLK_FSYS0_IP_USER, 4, 1),
+ MUX(CLK_MOUT_FSYS0_MAIN_USER, "mout_fsys0_main_user",
+ mout_fsys0_main_user_p, PLL_CON0_MUX_CLK_FSYS0_MAIN_USER, 4, 1),
+};
+
+static const struct samsung_div_clock cmu_fsys0_div_clks[] __initconst = {
+ DIV(CLK_DOUT_FSYS0_125, "dout_fsys0_125", "mout_fsys0_main_user",
+ CLK_CON_DIV_CLK_FSYS0_125, 0, 5),
+ DIV(CLK_DOUT_FSYS0_ADC, "dout_fsys0_adc", "mout_fsys0_main_user",
+ CLK_CON_DIV_CLK_FSYS0_ADC, 0, 7),
+ DIV(CLK_DOUT_FSYS0_BUS_300, "dout_fsys0_bus_300", "mout_fsys0_bus_user",
+ CLK_CON_DIV_CLK_FSYS0_BUS_300, 0, 4),
+ DIV(CLK_DOUT_FSYS0_EQOS0, "dout_fsys0_eqos0", "dout_fsys0_eqos_250",
+ CLK_CON_DIV_CLK_FSYS0_EQOS0, 0, 7),
+ DIV(CLK_DOUT_FSYS0_EQOS1, "dout_fsys0_eqos1", "dout_fsys0_eqos_250",
+ CLK_CON_DIV_CLK_FSYS0_EQOS1, 0, 7),
+ DIV(0, "dout_fsys0_eqos_250", "mout_fsys0_main_user",
+ CLK_CON_DIV_CLK_FSYS0_EQOS_250, 0, 4),
+ DIV(CLK_DOUT_FSYS0_MMC_CARD0, "dout_fsys0_mmc_card0", "mout_fsys0_ip_user",
+ CLK_CON_DIV_CLK_FSYS0_MMC_CARD0, 0, 10),
+ DIV(CLK_DOUT_FSYS0_MMC_CARD1, "dout_fsys0_mmc_card1", "mout_fsys0_ip_user",
+ CLK_CON_DIV_CLK_FSYS0_MMC_CARD1, 0, 10),
+ DIV(CLK_DOUT_FSYS0_MMC_CARD2, "dout_fsys0_mmc_card2", "mout_fsys0_ip_user",
+ CLK_CON_DIV_CLK_FSYS0_MMC_CARD2, 0, 10),
+ DIV(CLK_DOUT_FSYS0_QSPI, "dout_fsys0_qspi", "mout_fsys0_ip_user",
+ CLK_CON_DIV_CLK_FSYS0_QSPI, 0, 4),
+ DIV(CLK_DOUT_FSYS0_SFMC_NAND, "dout_fsys0_sfmc_nand", "mout_fsys0_ip_user",
+ CLK_CON_DIV_CLK_FSYS0_SFMC_NAND, 0, 4),
+};
+
+static const struct samsung_gate_clock cmu_fsys0_gate_clks[] __initconst = {
+ GATE(0, "adc_wrap_ipclkport_clk", "dout_fsys0_adc",
+ CLK_CON_DMYQCH_CON_ADC_WRAP_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "eqos_top0_ipclkport_aclk_i",
+ "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_CSR_I, "eqos_top0_ipclkport_clk_csr_i",
+ "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_PHASE_CLK_250,
+ "eqos_top0_ipclkport_i_rgmii_phase_clk_250",
+ "dout_fsys0_eqos_250", CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_TXCLK, "eqos_top0_ipclkport_i_rgmii_txclk",
+ "dout_fsys0_eqos0", CLK_CON_DMYQCH_CON_EQOS_TOP0_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_PHASE_CLK_250,
+ "eqos_top1_ipclkport_i_rgmii_phase_clk_250",
+ "dout_fsys0_eqos_250", CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_TXCLK, "eqos_top1_ipclkport_i_rgmii_txclk",
+ "dout_fsys0_eqos1", CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_ACLK_I, "eqos_top1_ipclkport_aclk_i",
+ "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_CLK_CSR_I, "eqos_top1_ipclkport_clk_csr_i",
+ "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_EQOS_TOP1_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_APB_S_PCLK, "i3c0_ipclkport_i_apb_s_pclk",
+ "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH, 1,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_CORE_CLK, "i3c0_ipclkport_i_core_clk",
+ "dout_fsys0_125", CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_DMA_CLK, "i3c0_ipclkport_i_dma_clk",
+ "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH,
+ 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_HDR_TX_CLK, "i3c0_ipclkport_i_hdr_tx_clk",
+ "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C0_QCH,
+ 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_APB_S_PCLK, "i3c1_ipclkport_i_apb_s_pclk",
+ "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH,
+ 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_CORE_CLK, "i3c1_ipclkport_i_core_clk",
+ "dout_fsys0_125", CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_DMA_CLK, "i3c1_ipclkport_i_dma_clk",
+ "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH,
+ 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_HDR_TX_CLK, "i3c1_ipclkport_i_hdr_tx_clk",
+ "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_FSYS0_I3C1_QCH,
+ 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_MMC0_IPCLKPORT_SDCLKIN, "mmc0_ipclkport_sdclkin",
+ "dout_fsys0_mmc_card0", CLK_CON_DMYQCH_CON_MMC0_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_MMC1_IPCLKPORT_SDCLKIN, "mmc1_ipclkport_sdclkin",
+ "dout_fsys0_mmc_card1", CLK_CON_DMYQCH_CON_MMC1_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_MMC2_IPCLKPORT_SDCLKIN, "mmc2_ipclkport_sdclkin",
+ "dout_fsys0_mmc_card2", CLK_CON_DMYQCH_CON_MMC2_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_QSPI_IPCLKPORT_HCLK, "qspi_ipclkport_hclk",
+ "dout_fsys0_bus_300", CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_QSPI_IPCLKPORT_SSI_CLK, "qspi_ipclkport_ssi_clk", "dout_fsys0_qspi",
+ CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_SFMC_IPCLKPORT_I_ACLK_NAND, "sfmc_ipclkport_i_aclk_nand",
+ "dout_fsys0_sfmc_nand", CLK_CON_DMYQCH_CON_SFMC_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_FSYS0_I2C0_IPCLKPORT_I_PCLK, "i2c0_ipclkport_i_pclk", "dout_fsys0_bus_300",
+ CLK_CON_FSYS0_I2C0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_I2C1_IPCLKPORT_I_PCLK, "i2c1_ipclkport_i_pclk", "dout_fsys0_bus_300",
+ CLK_CON_FSYS0_I2C1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_MMC0_IPCLKPORT_I_ACLK, "mmc0_ipclkport_i_aclk", "dout_fsys0_bus_300",
+ CLK_CON_MMC0_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_MMC1_IPCLKPORT_I_ACLK, "mmc1_ipclkport_i_aclk", "dout_fsys0_bus_300",
+ CLK_CON_MMC1_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_MMC2_IPCLKPORT_I_ACLK, "mmc2_ipclkport_i_aclk", "dout_fsys0_bus_300",
+ CLK_CON_MMC2_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0, "pwm_ipclkport_i_pclk", "dout_fsys0_bus_300",
+ CLK_CON_PWM_IPCLKPORT_I_PCLK_S0, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info cmu_fsys0_info __initconst = {
+ .mux_clks = cmu_fsys0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_fsys0_mux_clks),
+ .div_clks = cmu_fsys0_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cmu_fsys0_div_clks),
+ .gate_clks = cmu_fsys0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cmu_fsys0_gate_clks),
+ .nr_clk_ids = CMU_FSYS0_NR_CLK,
+ .clk_regs = cmu_fsys0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_fsys0_clk_regs),
+};
+
+/* Register Offset definitions for CMU_FSYS1 (0x14c10000) */
+#define PLL_LOCKTIME_PLL_FSYS1 0x0000
+#define PLL_CON0_MUX_CLK_FSYS1_BUS_USER 0x0100
+#define PLL_CON0_MUX_CLK_FSYS1_SCAN0_USER 0x0120
+#define PLL_CON0_MUX_CLK_FSYS1_SCAN1_USER 0x0140
+#define PLL_CON0_PLL_FSYS1 0x0160
+#define CLK_CON_DIV_CLK_FSYS1_200 0x1808
+#define CLK_CON_DIV_CLK_FSYS1_BUS_300 0x1810
+#define CLK_CON_DIV_CLK_FSYS1_OTP_MEM 0x1814
+#define CLK_CON_DIV_CLK_FSYS1_PCIE_PHY_REFCLK_SYSPLL 0x1818
+#define CLK_CON_FSYS1_UART0_IPCLKPORT_I_PCLK 0x202c
+#define CLK_CON_FSYS1_UART0_IPCLKPORT_I_SCLK_UART 0x2030
+#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300 0x205c
+#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC 0x2068
+#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC 0x206c
+#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC 0x2070
+#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC 0x2078
+#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC 0x2080
+#define CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC 0x2084
+#define CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 0x209c
+#define CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 0x20a0
+#define CLK_CON_XHB_AHBBR_FSYS1_IPCLKPORT_CLK 0x20a8
+#define CLK_CON_XHB_USB_IPCLKPORT_CLK 0x20ac
+#define CLK_CON_DMYQCH_CON_TZ400_QCH 0x3004
+#define CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_PHY_100 0x309c
+#define CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_0_0 0x3050
+#define CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_1_0 0x3058
+
+static const unsigned long cmu_fsys1_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_FSYS1,
+ PLL_CON0_MUX_CLK_FSYS1_BUS_USER,
+ PLL_CON0_MUX_CLK_FSYS1_SCAN0_USER,
+ PLL_CON0_MUX_CLK_FSYS1_SCAN1_USER,
+ PLL_CON0_PLL_FSYS1,
+ CLK_CON_DIV_CLK_FSYS1_200,
+ CLK_CON_DIV_CLK_FSYS1_BUS_300,
+ CLK_CON_DIV_CLK_FSYS1_OTP_MEM,
+ CLK_CON_DIV_CLK_FSYS1_PCIE_PHY_REFCLK_SYSPLL,
+ CLK_CON_FSYS1_UART0_IPCLKPORT_I_PCLK,
+ CLK_CON_FSYS1_UART0_IPCLKPORT_I_SCLK_UART,
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300,
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC,
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC,
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC,
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC,
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC,
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC,
+ CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20,
+ CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY,
+ CLK_CON_XHB_AHBBR_FSYS1_IPCLKPORT_CLK,
+ CLK_CON_XHB_USB_IPCLKPORT_CLK,
+ CLK_CON_DMYQCH_CON_TZ400_QCH,
+ CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_PHY_100,
+ CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_0_0,
+ CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_1_0
+};
+
+static const struct samsung_pll_rate_table artpec9_pll_fsys1_rates[] __initconst = {
+ PLL_35XX_RATE(25 * MHZ, 2000000000U, 80, 1, 0),
+};
+
+static const struct samsung_pll_clock cmu_fsys1_pll_clks[] __initconst = {
+ PLL(pll_a9fracm, CLK_FOUT_FSYS1_PLL, "fout_pll_fsys1", "fin_pll",
+ PLL_LOCKTIME_PLL_FSYS1, PLL_CON0_PLL_FSYS1, artpec9_pll_fsys1_rates),
+};
+
+PNAME(mout_fsys1_scan0_user_p) = { "fin_pll", "dout_clkcmu_fsys1_scan0" };
+PNAME(mout_fsys1_scan1_user_p) = { "fin_pll", "dout_clkcmu_fsys1_scan1" };
+PNAME(mout_fsys1_bus_user_p) = { "fin_pll", "dout_clkcmu_fsys1_bus" };
+PNAME(mout_fsys_pll_fsys_p) = { "fin_pll", "fout_pll_fsys1" };
+
+static const struct samsung_mux_clock cmu_fsys1_mux_clks[] __initconst = {
+ MUX(0, "mout_clk_pll_fsys1", mout_fsys_pll_fsys_p, PLL_CON0_PLL_FSYS1, 4, 1),
+ MUX(CLK_MOUT_FSYS1_SCAN0_USER, "mout_fsys1_scan0_user",
+ mout_fsys1_scan0_user_p, PLL_CON0_MUX_CLK_FSYS1_SCAN0_USER, 4, 1),
+ MUX(CLK_MOUT_FSYS1_SCAN1_USER, "mout_fsys1_scan1_user",
+ mout_fsys1_scan1_user_p, PLL_CON0_MUX_CLK_FSYS1_SCAN1_USER, 4, 1),
+ MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
+ mout_fsys1_bus_user_p, PLL_CON0_MUX_CLK_FSYS1_BUS_USER, 4, 1),
+};
+
+static const struct samsung_div_clock cmu_fsys1_div_clks[] __initconst = {
+ DIV(CLK_DOUT_FSYS1_200, "dout_fsys1_200", "mout_clk_pll_fsys1",
+ CLK_CON_DIV_CLK_FSYS1_200, 0, 4),
+ DIV(CLK_DOUT_FSYS1_BUS_300, "dout_fsys1_bus_300", "mout_fsys1_bus_user",
+ CLK_CON_DIV_CLK_FSYS1_BUS_300, 0, 4),
+ DIV(CLK_DOUT_FSYS1_OTP_MEM, "dout_fsys1_otp_mem", "fin_pll",
+ CLK_CON_DIV_CLK_FSYS1_OTP_MEM, 0, 4),
+ DIV(CLK_DOUT_FSYS1_PCIE_PHY_REFCLK_SYSPLL, "dout_fsys1_pcie_phy_refclk_syspll",
+ "mout_clk_pll_fsys1", CLK_CON_DIV_CLK_FSYS1_PCIE_PHY_REFCLK_SYSPLL, 0, 5),
+};
+
+static const struct samsung_gate_clock cmu_fsys1_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_100,
+ "pcie_top_ipclkport_pcie_phy_apb2cr_pclk_100", "dout_fsys1_pcie_phy_refclk_syspll",
+ CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_PHY_100, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(0, "tzc400_ipclkport_aclk0", "mout_fsys1_bus_user",
+ CLK_CON_DMYQCH_CON_TZ400_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(0, "tzc400_ipclkport_aclk1", "mout_fsys1_bus_user",
+ CLK_CON_DMYQCH_CON_TZ400_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(0, "tzc400_ipclkport_pclk", "dout_fsys1_bus_300",
+ CLK_CON_DMYQCH_CON_TZ400_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_UART0_PCLK, "uart", "dout_fsys1_bus_300",
+ CLK_CON_FSYS1_UART0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_UART0_SCLK_UART, "clk_uart_baud0", "dout_fsys1_200",
+ CLK_CON_FSYS1_UART0_IPCLKPORT_I_SCLK_UART, 21,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300,
+ "pcie_top_ipclkport_pcie_phy_apb2cr_pclk_300", "dout_fsys1_bus_300",
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300, 21,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC,
+ "pcie_top_ipclkport_pcie_sub_con_x1_dbi_aclk_soc", "dout_fsys1_bus_300",
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC,
+ 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC,
+ "pcie_top_ipclkport_pcie_sub_con_x1_mstr_aclk_soc", "mout_fsys1_bus_user",
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC,
+ 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC,
+ "pcie_top_ipclkport_pcie_sub_con_x1_slv_aclk_soc", "mout_fsys1_bus_user",
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC,
+ 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC,
+ "pcie_top_ipclkport_pcie_sub_con_x2_dbi_aclk_soc", "dout_fsys1_bus_300",
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC,
+ 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC,
+ "pcie_top_ipclkport_pcie_sub_con_x2_mstr_aclk_soc", "mout_fsys1_bus_user",
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC,
+ 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC,
+ "pcie_top_ipclkport_pcie_sub_con_x2_slv_aclk_soc", "mout_fsys1_bus_user",
+ CLK_CON_PCIE_TOP_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC,
+ 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20,
+ "usb20drd_ipclkport_aclk_phyctrl_20", "dout_fsys1_bus_300",
+ CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20,
+ 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, "usb20drd_ipclkport_bus_clk_early",
+ "dout_fsys1_bus_300", CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY,
+ 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_XHB_AHBBR_FSYS1_IPCLKPORT_CLK, "xhb_ahbbr_fsys1_ipclkport_clk",
+ "dout_fsys1_bus_300", CLK_CON_XHB_AHBBR_FSYS1_IPCLKPORT_CLK,
+ 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK, "xhb_usb_ipclkport_clk", "dout_fsys1_bus_300",
+ CLK_CON_XHB_USB_IPCLKPORT_CLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(0, "qch_con_mmu_fsys1_qch_u_tbu_0_0", "mout_fsys1_bus_user",
+ CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_0_0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(0, "qch_con_mmu_fsys1_qch_u_tbu_1_0", "mout_fsys1_bus_user",
+ CLK_CON_QCH_CON_MMU_FSYS1_QCH_U_TBU_1_0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info cmu_fsys1_info __initconst = {
+ .pll_clks = cmu_fsys1_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cmu_fsys1_pll_clks),
+ .mux_clks = cmu_fsys1_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_fsys1_mux_clks),
+ .div_clks = cmu_fsys1_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cmu_fsys1_div_clks),
+ .gate_clks = cmu_fsys1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cmu_fsys1_gate_clks),
+ .nr_clk_ids = CMU_FSYS1_NR_CLK,
+ .clk_regs = cmu_fsys1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_fsys1_clk_regs),
+};
+
+/* Register Offset definitions for CMU_IMEM (0x10010000) */
+#define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100
+#define PLL_CON0_MUX_CLK_IMEM_CA5_USER 0x0120
+#define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0140
+#define PLL_CON0_MUX_CLK_IMEM_SSS_USER 0x0160
+#define CLK_CON_MCT0_IPCLKPORT_PCLK 0x20b4
+#define CLK_CON_MCT1_IPCLKPORT_PCLK 0x20b8
+#define CLK_CON_MCT2_IPCLKPORT_PCLK 0x20bc
+#define CLK_CON_MCT3_IPCLKPORT_PCLK 0x20c0
+#define CLK_CON_TMU_APB_IPCLKPORT_PCLK 0x20d4
+#define CLK_CON_DMYQCH_CON_CA5_0_QCH 0x3008
+#define CLK_CON_DMYQCH_CON_CA5_1_QCH 0x3018
+#define CLK_CON_DMYQCH_CON_INTMEM_QCH 0x3020
+#define CLK_CON_QCH_CON_GIC_CA55_QCHANNEL_SLAVE_0 0x306c
+#define CLK_CON_QCH_CON_GIC_CA5_0_QCH 0x3078
+#define CLK_CON_QCH_CON_GIC_CA5_1_QCH 0x307c
+#define CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_0_0 0x30ac
+#define CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_1_0 0x30b4
+
+static const unsigned long cmu_imem_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLK_IMEM_ACLK_USER,
+ PLL_CON0_MUX_CLK_IMEM_CA5_USER,
+ PLL_CON0_MUX_CLK_IMEM_JPEG_USER,
+ PLL_CON0_MUX_CLK_IMEM_SSS_USER,
+ CLK_CON_MCT0_IPCLKPORT_PCLK,
+ CLK_CON_MCT1_IPCLKPORT_PCLK,
+ CLK_CON_MCT2_IPCLKPORT_PCLK,
+ CLK_CON_MCT3_IPCLKPORT_PCLK,
+ CLK_CON_TMU_APB_IPCLKPORT_PCLK,
+ CLK_CON_DMYQCH_CON_CA5_0_QCH,
+ CLK_CON_DMYQCH_CON_CA5_1_QCH,
+ CLK_CON_DMYQCH_CON_INTMEM_QCH,
+ CLK_CON_QCH_CON_GIC_CA55_QCHANNEL_SLAVE_0,
+ CLK_CON_QCH_CON_GIC_CA5_0_QCH,
+ CLK_CON_QCH_CON_GIC_CA5_1_QCH,
+ CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_0_0,
+ CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_1_0
+};
+
+PNAME(mout_imem_aclk_user_p) = { "fin_pll", "dout_clkcmu_imem_aclk" };
+PNAME(mout_imem_ca5_user_p) = { "fin_pll", "dout_clkcmu_imem_ca5" };
+PNAME(mout_imem_jpeg_user_p) = { "fin_pll", "dout_clkcmu_imem_jpeg" };
+PNAME(mout_imem_sss_user_p) = { "fin_pll", "dout_clkcmu_imem_sss" };
+
+static const struct samsung_mux_clock cmu_imem_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_IMEM_ACLK_USER, "mout_clk_imem_aclk_user",
+ mout_imem_aclk_user_p, PLL_CON0_MUX_CLK_IMEM_ACLK_USER, 4, 1),
+ MUX(CLK_MOUT_IMEM_CA5_USER, "mout_clk_imem_ca5_user",
+ mout_imem_ca5_user_p, PLL_CON0_MUX_CLK_IMEM_CA5_USER, 4, 1),
+ MUX(CLK_MOUT_IMEM_SSS_USER, "mout_clk_imem_sss_user",
+ mout_imem_sss_user_p, PLL_CON0_MUX_CLK_IMEM_SSS_USER, 4, 1),
+ MUX(CLK_MOUT_IMEM_JPEG_USER, "mout_clk_imem_jpeg_user",
+ mout_imem_jpeg_user_p, PLL_CON0_MUX_CLK_IMEM_JPEG_USER, 4, 1),
+};
+
+static const struct samsung_fixed_factor_clock imem_ffactor_clks[] __initconst = {
+ FFACTOR(CLK_DOUT_IMEM_PCLK, "dout_clk_imem_pclk", "mout_clk_imem_aclk_user", 1, 2, 0),
+};
+
+static const struct samsung_gate_clock cmu_imem_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_IMEM_CA5_0_IPCLKPORT_ATCLK, "ca5_0_ipclkport_atclk",
+ "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_0_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_IMEM_CA5_0_IPCLKPORT_CLKIN, "ca5_0_ipclkport_clkin",
+ "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_0_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_IMEM_CA5_0_IPCLKPORT_PCLK_DBG, "ca5_0_ipclkport_pclk_dbg",
+ "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_0_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_IMEM_CA5_1_IPCLKPORT_ATCLK, "ca5_1_ipclkport_atclk",
+ "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_1_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_IMEM_CA5_1_IPCLKPORT_CLKIN, "ca5_1_ipclkport_clkin",
+ "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_1_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_IMEM_CA5_1_IPCLKPORT_PCLK_DBG, "ca5_1_ipclkport_pclk_dbg",
+ "mout_clk_imem_ca5_user", CLK_CON_DMYQCH_CON_CA5_1_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(0, "intmem_ipclkport_aclk", "mout_clk_imem_aclk_user",
+ CLK_CON_DMYQCH_CON_INTMEM_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_IMEM_MCT0_PCLK, "mct0", "dout_clk_imem_pclk",
+ CLK_CON_MCT0_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_IMEM_MCT1_PCLK, "mct1", "dout_clk_imem_pclk",
+ CLK_CON_MCT1_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_IMEM_MCT2_PCLK, "mct2", "dout_clk_imem_pclk",
+ CLK_CON_MCT2_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_IMEM_MCT3_PCLK, "mct3", "dout_clk_imem_pclk",
+ CLK_CON_MCT3_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_IMEM_PCLK_TMU0_APBIF, "tmu_apb_ipclkport_pclk", "dout_clk_imem_pclk",
+ CLK_CON_TMU_APB_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(0, "qch_con_gic_ca55_qchannel_slave_0", "dout_clk_imem_pclk",
+ CLK_CON_QCH_CON_GIC_CA55_QCHANNEL_SLAVE_0, 1,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(0, "qch_con_gic_ca5_0_qch", "dout_clk_imem_pclk",
+ CLK_CON_QCH_CON_GIC_CA5_0_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(0, "qch_con_gic_ca5_1_qch", "dout_clk_imem_pclk",
+ CLK_CON_QCH_CON_GIC_CA5_1_QCH, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(0, "qch_con_mmu_imem_qch_u_tbu_0_0", "mout_clk_imem_ca5_user",
+ CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_0_0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(0, "qch_con_mmu_imem_qch_u_tbu_1_0", "mout_clk_imem_ca5_user",
+ CLK_CON_QCH_CON_MMU_IMEM_QCH_U_TBU_1_0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info cmu_imem_info __initconst = {
+ .fixed_factor_clks = imem_ffactor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(imem_ffactor_clks),
+ .mux_clks = cmu_imem_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_imem_mux_clks),
+ .gate_clks = cmu_imem_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cmu_imem_gate_clks),
+ .nr_clk_ids = CMU_IMEM_NR_CLK,
+ .clk_regs = cmu_imem_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_imem_clk_regs),
+};
+
+static void __init artpec9_cmu_imem_init(struct device_node *np)
+{
+ exynos_arm64_register_cmu(NULL, np, &cmu_imem_info);
+}
+
+CLK_OF_DECLARE(artpec9_cmu_imem, "axis,artpec9-cmu-imem", artpec9_cmu_imem_init);
+
+/* Register Offset definitions for CMU_PERI (0x14010000) */
+#define PLL_CON0_MUX_CLK_PERI_DISP_USER 0x0100
+#define PLL_CON0_MUX_CLK_PERI_IP_USER 0x0120
+#define CLK_CON_DIV_CLK_PERI_125 0x1800
+#define CLK_CON_DIV_CLK_PERI_PCLK 0x180c
+#define CLK_CON_DIV_CLK_PERI_SPI 0x1810
+#define CLK_CON_DIV_CLK_PERI_UART1 0x1814
+#define CLK_CON_DIV_CLK_PERI_UART2 0x1818
+#define CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 0x2000
+#define CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK 0x202c
+#define CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK 0x2030
+#define CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK 0x2054
+#define CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI 0x2058
+#define CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK 0x205c
+#define CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART 0x2060
+#define CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK 0x2064
+#define CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART 0x2068
+#define CLK_CON_DMYQCH_CON_DMA4DSIM_QCH 0x3000
+#define CLK_CON_DMYQCH_CON_PERI_I3C2_QCH 0x3004
+#define CLK_CON_DMYQCH_CON_PERI_I3C3_QCH 0x3008
+
+static const unsigned long cmu_peri_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLK_PERI_DISP_USER,
+ PLL_CON0_MUX_CLK_PERI_IP_USER,
+ CLK_CON_DIV_CLK_PERI_125,
+ CLK_CON_DIV_CLK_PERI_PCLK,
+ CLK_CON_DIV_CLK_PERI_SPI,
+ CLK_CON_DIV_CLK_PERI_UART1,
+ CLK_CON_DIV_CLK_PERI_UART2,
+ CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS,
+ CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK,
+ CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK,
+ CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK,
+ CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI,
+ CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK,
+ CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART,
+ CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK,
+ CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART,
+ CLK_CON_DMYQCH_CON_DMA4DSIM_QCH,
+ CLK_CON_DMYQCH_CON_PERI_I3C2_QCH,
+ CLK_CON_DMYQCH_CON_PERI_I3C3_QCH,
+};
+
+PNAME(mout_peri_ip_user_p) = { "fin_pll", "dout_clkcmu_peri_ip" };
+PNAME(mout_peri_disp_user_p) = { "fin_pll", "dout_clkcmu_peri_disp" };
+
+static const struct samsung_mux_clock cmu_peri_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_PERI_IP_USER, "mout_peri_ip_user", mout_peri_ip_user_p,
+ PLL_CON0_MUX_CLK_PERI_IP_USER, 4, 1),
+ MUX(CLK_MOUT_PERI_DISP_USER, "mout_peri_disp_user", mout_peri_disp_user_p,
+ PLL_CON0_MUX_CLK_PERI_DISP_USER, 4, 1),
+};
+
+static const struct samsung_div_clock cmu_peri_div_clks[] __initconst = {
+ DIV(CLK_DOUT_PERI_125, "dout_peri_125", "mout_peri_ip_user",
+ CLK_CON_DIV_CLK_PERI_125, 0, 4),
+ DIV(CLK_DOUT_PERI_PCLK, "dout_peri_pclk", "mout_peri_ip_user",
+ CLK_CON_DIV_CLK_PERI_PCLK, 0, 4),
+ DIV(CLK_DOUT_PERI_SPI, "dout_peri_spi", "mout_peri_ip_user",
+ CLK_CON_DIV_CLK_PERI_SPI, 0, 13),
+ DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "mout_peri_ip_user",
+ CLK_CON_DIV_CLK_PERI_UART1, 0, 10),
+ DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "mout_peri_ip_user",
+ CLK_CON_DIV_CLK_PERI_UART2, 0, 10),
+};
+
+static const struct samsung_gate_clock cmu_peri_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK, "dma4dsim_ipclkport_clk_apb_clk",
+ "dout_peri_pclk", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK, "dma4dsim_ipclkport_clk_axi_clk",
+ "mout_peri_disp_user", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I3C2_IPCLKPORT_I_APB_S_PCLK, "peri_i3c2_ipclkport_i_apb_s_pclk",
+ "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C2_QCH, 1,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_I3C2_IPCLKPORT_I_CORE_CLK, "peri_i3c2_ipclkport_i_core_clk",
+ "dout_peri_125", CLK_CON_DMYQCH_CON_PERI_I3C2_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I3C2_IPCLKPORT_I_DMA_CLK, "peri_i3c2_ipclkport_i_dma_clk",
+ "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C2_QCH, 1,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_I3C2_IPCLKPORT_I_HDR_TX_CLK, "peri_i3c2_ipclkport_i_hdr_tx_clk",
+ "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C2_QCH, 1,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_I3C3_IPCLKPORT_I_APB_S_PCLK, "peri_i3c3_ipclkport_i_apb_s_pclk",
+ "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C3_QCH, 1,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_I3C3_IPCLKPORT_I_CORE_CLK, "peri_i3c3_ipclkport_i_core_clk",
+ "dout_peri_125", CLK_CON_DMYQCH_CON_PERI_I3C3_QCH, 1, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_PERI_I3C3_IPCLKPORT_I_DMA_CLK, "peri_i3c3_ipclkport_i_dma_clk",
+ "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C3_QCH, 1,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_I3C3_IPCLKPORT_I_HDR_TX_CLK, "peri_i3c3_ipclkport_i_hdr_tx_clk",
+ "dout_peri_pclk", CLK_CON_DMYQCH_CON_PERI_I3C3_QCH, 1,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, "apb_async_dsim_ipclkport_pclks",
+ "dout_peri_pclk", CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, 21,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK, "peri_i2c2_ipclkport_i_pclk",
+ "dout_peri_pclk", CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK, 21,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK, "peri_i2c3_ipclkport_i_pclk",
+ "dout_peri_pclk", CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK, 21,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_SPI0_PCLK, "peri_spi0_ipclkport_i_pclk",
+ "dout_peri_pclk", CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK, 21,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_SPI0_SCLK_SPI, "peri_spi0_ipclkport_i_sclk_spi",
+ "dout_peri_spi", CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI, 21,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_UART1_PCLK, "uart1", "dout_peri_pclk",
+ CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_UART1_SCLK_UART, "clk_uart_baud1", "dout_peri_uart1",
+ CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART, 21,
+ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_UART2_PCLK, "uart2", "dout_peri_pclk",
+ CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERI_UART2_SCLK_UART, "clk_uart_baud2", "dout_peri_uart2",
+ CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART,
+ 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info cmu_peri_info __initconst = {
+ .mux_clks = cmu_peri_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_peri_mux_clks),
+ .div_clks = cmu_peri_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cmu_peri_div_clks),
+ .gate_clks = cmu_peri_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cmu_peri_gate_clks),
+ .nr_clk_ids = CMU_PERI_NR_CLK,
+ .clk_regs = cmu_peri_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_peri_clk_regs),
+};
+
+static int __init artpec9_cmu_probe(struct platform_device *pdev)
+{
+ const struct samsung_cmu_info *info;
+ struct device *dev = &pdev->dev;
+
+ info = of_device_get_match_data(dev);
+ exynos_arm64_register_cmu(dev, dev->of_node, info);
+
+ return 0;
+}
+
+static const struct of_device_id artpec9_cmu_of_match[] = {
+ {
+ .compatible = "axis,artpec9-cmu-cmu",
+ .data = &cmu_cmu_info,
+ }, {
+ .compatible = "axis,artpec9-cmu-bus",
+ .data = &cmu_bus_info,
+ }, {
+ .compatible = "axis,artpec9-cmu-core",
+ .data = &cmu_core_info,
+ }, {
+ .compatible = "axis,artpec9-cmu-cpucl",
+ .data = &cmu_cpucl_info,
+ }, {
+ .compatible = "axis,artpec9-cmu-fsys0",
+ .data = &cmu_fsys0_info,
+ }, {
+ .compatible = "axis,artpec9-cmu-fsys1",
+ .data = &cmu_fsys1_info,
+ }, {
+ .compatible = "axis,artpec9-cmu-peri",
+ .data = &cmu_peri_info,
+ }, {
+ },
+};
+
+static struct platform_driver artpec9_cmu_driver __refdata = {
+ .driver = {
+ .name = "artpec9-cmu",
+ .of_match_table = artpec9_cmu_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = artpec9_cmu_probe,
+};
+
+static int __init artpec9_cmu_init(void)
+{
+ return platform_driver_register(&artpec9_cmu_driver);
+}
+core_initcall(artpec9_cmu_init);
diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index 56f27697c76b..eb9c80b60225 100644
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -19,7 +19,7 @@
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (CLK_DOUT_CPUCL1_SWITCH + 1)
-#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
+#define CLKS_NR_APM (CLK_GOUT_MAILBOX_APM_AP_PCLK + 1)
#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
#define CLKS_NR_CPUCL0 (CLK_CLUSTER0_SCLK + 1)
@@ -604,6 +604,7 @@ CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
#define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM_AP_PCLK 0x2060
#define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
#define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0
@@ -628,6 +629,7 @@ static const unsigned long apm_clk_regs[] __initconst = {
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,
+ CLK_CON_GAT_GOUT_APM_MAILBOX_APM_AP_PCLK,
};
/* List of parent clocks for Muxes in CMU_APM */
@@ -698,6 +700,9 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_MAILBOX_APM_AP_PCLK, "gout_mailbox_apm_ap_pclk",
+ "dout_apm_func",
+ CLK_CON_GAT_GOUT_APM_MAILBOX_APM_AP_PCLK, 21, 0, 0),
};
static const struct samsung_cmu_info apm_cmu_info __initconst = {
diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c
index d0617c7fff3a..04cd40c71d13 100644
--- a/drivers/clk/samsung/clk-exynosautov920.c
+++ b/drivers/clk/samsung/clk-exynosautov920.c
@@ -30,6 +30,7 @@
#define CLKS_NR_M2M (CLK_DOUT_M2M_NOCP + 1)
#define CLKS_NR_MFC (CLK_DOUT_MFC_NOCP + 1)
#define CLKS_NR_MFD (CLK_DOUT_MFD_NOCP + 1)
+#define CLKS_NR_G3D (CLK_MOUT_G3D_NOCP_USER + 1)
/* ---- CMU_TOP ------------------------------------------------------------ */
@@ -1942,6 +1943,54 @@ static const struct samsung_cmu_info mfd_cmu_info __initconst = {
.clk_name = "noc",
};
+/* ---- CMU_G3D --------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_G3D (0x1a000000) */
+#define PLL_LOCKTIME_PLL_G3D 0x0
+#define PLL_CON3_PLL_G3D 0x10c
+#define CLK_CON_MUX_MUX_CLK_G3D_NOC 0x1000
+#define PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER 0x600
+#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x610
+
+static const unsigned long g3d_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_G3D,
+ PLL_CON3_PLL_G3D,
+ CLK_CON_MUX_MUX_CLK_G3D_NOC,
+ PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER,
+ PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER,
+};
+
+static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
+ /* CMU_G3D_PLL */
+ PLL(pll_531x, FOUT_PLL_G3D, "fout_pll_g3d", "oscclk",
+ PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
+};
+
+/* List of parent clocks for Muxes in CMU_G3D */
+PNAME(mout_clk_g3d_noc_p) = { "oscclk", "fout_pll_g3d", "mout_clkcmu_g3d_switch_user"};
+PNAME(mout_clkcmu_g3d_switch_user_p) = { "oscclk", "dout_clkcmu_g3d_switch" };
+PNAME(mout_clkcmu_g3d_nocp_user_p) = { "oscclk", "dout_clkcmu_g3d_nocp" };
+
+static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_G3D_NOC, "mout_clk_g3d_noc",
+ mout_clk_g3d_noc_p, CLK_CON_MUX_MUX_CLK_G3D_NOC, 0, 2),
+ MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_clkcmu_g3d_switch_user",
+ mout_clkcmu_g3d_switch_user_p, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1),
+ MUX(CLK_MOUT_G3D_NOCP_USER, "mout_clkcmu_g3d_nocp_user",
+ mout_clkcmu_g3d_nocp_user_p, PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER, 4, 1),
+};
+
+static const struct samsung_cmu_info g3d_cmu_info __initconst = {
+ .pll_clks = g3d_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
+ .mux_clks = g3d_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
+ .nr_clk_ids = CLKS_NR_G3D,
+ .clk_regs = g3d_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
+ .clk_name = "noc",
+};
+
static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
{
const struct samsung_cmu_info *info;
@@ -1981,6 +2030,9 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = {
}, {
.compatible = "samsung,exynosautov920-cmu-mfd",
.data = &mfd_cmu_info,
+ }, {
+ .compatible = "samsung,exynosautov920-cmu-g3d",
+ .data = &g3d_cmu_info,
},
{ }
};
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index 44a8ecd332fd..d2bcd3a9daf8 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -339,7 +339,7 @@
#define GENERALIO_ACD_CHANNEL_3 0x3f0c
#define GENERALIO_ACD_MASK 0x3f14
-static const unsigned long cmu_top_clk_regs[] __initconst = {
+static const unsigned long top_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_SHARED0,
PLL_LOCKTIME_PLL_SHARED1,
PLL_LOCKTIME_PLL_SHARED2,
@@ -638,7 +638,7 @@ static const unsigned long cmu_top_clk_regs[] __initconst = {
GENERALIO_ACD_MASK,
};
-static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
+static const struct samsung_pll_clock top_pll_clks[] __initconst = {
/* CMU_TOP_PURECLKCOMP */
PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
@@ -952,7 +952,7 @@ PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1",
* For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC
*/
-static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
+static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
PLL_CON0_PLL_SHARED0, 4, 1),
MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
@@ -1108,7 +1108,7 @@ static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
};
-static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
+static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",
@@ -1253,13 +1253,13 @@ static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
"mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
};
-static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {
+static const struct samsung_fixed_factor_clock top_ffactor_clks[] __initconst = {
FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg",
"gout_cmu_hsi0_usbdpdbg", 1, 4, 0),
FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),
};
-static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
+static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost",
"mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0),
GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost",
@@ -1425,19 +1425,19 @@ static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
};
static const struct samsung_cmu_info top_cmu_info __initconst = {
- .pll_clks = cmu_top_pll_clks,
- .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks),
- .mux_clks = cmu_top_mux_clks,
- .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks),
- .div_clks = cmu_top_div_clks,
- .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks),
- .fixed_factor_clks = cmu_top_ffactor,
- .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor),
- .gate_clks = cmu_top_gate_clks,
- .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks),
+ .pll_clks = top_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
+ .mux_clks = top_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
+ .div_clks = top_div_clks,
+ .nr_div_clks = ARRAY_SIZE(top_div_clks),
+ .fixed_factor_clks = top_ffactor_clks,
+ .nr_fixed_factor_clks = ARRAY_SIZE(top_ffactor_clks),
+ .gate_clks = top_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
.nr_clk_ids = CLKS_NR_TOP,
- .clk_regs = cmu_top_clk_regs,
- .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs),
+ .clk_regs = top_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
.auto_clock_gate = true,
.gate_dbg_offset = GS101_GATE_DBG_OFFSET,
.option_offset = CMU_CMU_TOP_CONTROLLER_OPTION,
@@ -2434,15 +2434,15 @@ PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll",
"dout_hsi0_usb31drd",
"fout_usb_pll" };
-static const struct samsung_pll_rate_table cmu_hsi0_usb_pll_rates[] __initconst = {
+static const struct samsung_pll_rate_table hsi0_usb_pll_rates[] __initconst = {
PLL_35XX_RATE(24576000, 19200000, 150, 6, 5),
{ /* sentinel */ }
};
-static const struct samsung_pll_clock cmu_hsi0_pll_clks[] __initconst = {
+static const struct samsung_pll_clock hsi0_pll_clks[] __initconst = {
PLL(pll_0518x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
PLL_LOCKTIME_PLL_USB, PLL_CON3_PLL_USB,
- cmu_hsi0_usb_pll_rates),
+ hsi0_usb_pll_rates),
};
static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
@@ -2660,8 +2660,8 @@ static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst = {
};
static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
- .pll_clks = cmu_hsi0_pll_clks,
- .nr_pll_clks = ARRAY_SIZE(cmu_hsi0_pll_clks),
+ .pll_clks = hsi0_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(hsi0_pll_clks),
.mux_clks = hsi0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
.div_clks = hsi0_div_clks,
@@ -2791,7 +2791,7 @@ static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
#define QCH_CON_UFS_EMBD_QCH_FMP 0x3094
#define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00
-static const unsigned long cmu_hsi2_clk_regs[] __initconst = {
+static const unsigned long hsi2_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER,
PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER,
PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
@@ -3166,8 +3166,8 @@ static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
.gate_clks = hsi2_gate_clks,
.nr_gate_clks = ARRAY_SIZE(hsi2_gate_clks),
.nr_clk_ids = CLKS_NR_HSI2,
- .clk_regs = cmu_hsi2_clk_regs,
- .nr_clk_regs = ARRAY_SIZE(cmu_hsi2_clk_regs),
+ .clk_regs = hsi2_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(hsi2_clk_regs),
.sysreg_clk_regs = dcrg_memclk_sysreg,
.nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
.clk_name = "bus",
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 026ac556fa2e..fdb84bcec912 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -201,6 +201,9 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
#define PLL35XX_LOCK_STAT_SHIFT (29)
#define PLL35XX_ENABLE_SHIFT (31)
+/* A9FRACM is similar to PLL35xx, except that MDIV is bit different */
+#define PLLA9FRACM_MDIV_SHIFT (14)
+
static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -209,7 +212,12 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
u64 fvco = parent_rate;
pll_con = readl_relaxed(pll->con_reg);
- mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+
+ if (pll->type == pll_a9fracm)
+ mdiv = (pll_con >> PLLA9FRACM_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+ else
+ mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+
pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
@@ -219,12 +227,15 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
return (unsigned long)fvco;
}
-static inline bool samsung_pll35xx_mp_change(
- const struct samsung_pll_rate_table *rate, u32 pll_con)
+static inline bool samsung_pll35xx_mp_change(u32 pll_type,
+ const struct samsung_pll_rate_table *rate, u32 pll_con)
{
u32 old_mdiv, old_pdiv;
- old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+ if (pll_type == pll_a9fracm)
+ old_mdiv = (pll_con >> PLLA9FRACM_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+ else
+ old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv);
@@ -236,6 +247,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
struct samsung_clk_pll *pll = to_clk_pll(hw);
const struct samsung_pll_rate_table *rate;
u32 tmp;
+ u32 mdiv_shift;
+
+ if (pll->type == pll_a9fracm)
+ mdiv_shift = PLLA9FRACM_MDIV_SHIFT;
+ else
+ mdiv_shift = PLL35XX_MDIV_SHIFT;
/* Get required rate settings from table */
rate = samsung_get_pll_settings(pll, drate);
@@ -247,7 +264,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
tmp = readl_relaxed(pll->con_reg);
- if (!(samsung_pll35xx_mp_change(rate, tmp))) {
+ if (!(samsung_pll35xx_mp_change(pll->type, rate, tmp))) {
/* If only s change, change just s value only*/
tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
@@ -257,7 +274,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
}
/* Set PLL lock time. */
- if (pll->type == pll_142xx || pll->type == pll_1017x)
+ if (pll->type == pll_142xx || pll->type == pll_1017x || pll->type == pll_a9fracm)
writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
pll->lock_reg);
else
@@ -265,10 +282,10 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
pll->lock_reg);
/* Change PLL PMS values */
- tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
+ tmp &= ~((PLL35XX_MDIV_MASK << mdiv_shift) |
(PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
- tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
+ tmp |= (rate->mdiv << mdiv_shift) |
(rate->pdiv << PLL35XX_PDIV_SHIFT) |
(rate->sdiv << PLL35XX_SDIV_SHIFT);
writel_relaxed(tmp, pll->con_reg);
@@ -1428,6 +1445,149 @@ static const struct clk_ops samsung_pll1031x_clk_min_ops = {
.recalc_rate = samsung_pll1031x_recalc_rate,
};
+/*
+ * PLLA9FRACO Clock Type
+ */
+#define PLLA9FRACO_LOCK_FACTOR (500)
+
+#define PLLA9FRACO_MDIV_MASK (0x3ff)
+#define PLLA9FRACO_PDIV_MASK (0x3f)
+#define PLLA9FRACO_SDIV_MASK (0x7)
+#define PLLA9FRACO_MDIV_SHIFT (14)
+#define PLLA9FRACO_PDIV_SHIFT (8)
+#define PLLA9FRACO_SDIV_SHIFT (0)
+
+#define PLLA9FRACO_PLL_CON5_DIV_FRAC (0x14)
+#define PLLA9FRACO_KDIV_MASK (0xffffff)
+#define PLLA9FRACO_KDIV_SHIFT (0)
+#define PLLA9FRACO_DAC_MODE BIT(30)
+#define PLLA9FRACO_DSM_EN BIT(31)
+#define PLLA9FRACO_FOUTPOSTDIVEN BIT(3)
+#define PLLA9FRACO_MUX_SEL BIT(4)
+#define PLLA9FRACO_ENABLE_SHIFT (31)
+#define PLLA9FRACO_LOCK_STAT_SHIFT (29)
+
+static unsigned long samsung_a9fraco_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 pll_con0, pll_con5;
+ u64 mdiv, pdiv, sdiv, kdiv;
+ u64 fvco = parent_rate;
+
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con5 = readl_relaxed(pll->con_reg + PLLA9FRACO_PLL_CON5_DIV_FRAC);
+ mdiv = (pll_con0 >> PLLA9FRACO_MDIV_SHIFT) & PLLA9FRACO_MDIV_MASK;
+ pdiv = (pll_con0 >> PLLA9FRACO_PDIV_SHIFT) & PLLA9FRACO_PDIV_MASK;
+ sdiv = (pll_con0 >> PLLA9FRACO_SDIV_SHIFT) & PLLA9FRACO_SDIV_MASK;
+ kdiv = (pll_con5 & PLLA9FRACO_KDIV_MASK);
+
+ /* fvco = fref * (M + K/2^24) / p * (S+1) */
+ fvco *= mdiv;
+ fvco = (fvco << 24) + kdiv;
+ fvco = div64_u64(fvco, ((pdiv * (sdiv + 1)) << 24));
+
+ return (unsigned long)fvco;
+}
+
+static bool samsung_a9fraco_mpk_change(u32 pll_con0, u32 pll_con5,
+ const struct samsung_pll_rate_table *rate)
+{
+ u32 old_mdiv, old_pdiv, old_kdiv;
+
+ old_mdiv = (pll_con0 >> PLLA9FRACO_MDIV_SHIFT) & PLLA9FRACO_MDIV_MASK;
+ old_pdiv = (pll_con0 >> PLLA9FRACO_PDIV_SHIFT) & PLLA9FRACO_PDIV_MASK;
+ old_kdiv = (pll_con5 >> PLLA9FRACO_KDIV_SHIFT) & PLLA9FRACO_KDIV_MASK;
+
+ return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv || old_kdiv != rate->kdiv);
+}
+
+static int samsung_a9fraco_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 con0, con5;
+ int ret;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ con0 = readl_relaxed(pll->con_reg);
+ con5 = readl_relaxed(pll->con_reg + PLLA9FRACO_PLL_CON5_DIV_FRAC);
+
+ if (!(samsung_a9fraco_mpk_change(con0, con5, rate))) {
+ /* If only s change, change just s value only */
+ con0 &= ~(PLLA9FRACO_SDIV_MASK << PLLA9FRACO_SDIV_SHIFT);
+ con0 |= rate->sdiv << PLLA9FRACO_SDIV_SHIFT;
+ writel_relaxed(con0, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Select OSCCLK (0) */
+ con0 = readl_relaxed(pll->con_reg);
+ con0 &= ~(PLLA9FRACO_MUX_SEL);
+ writel_relaxed(con0, pll->con_reg);
+
+ /* Disable PLL */
+ con0 &= ~BIT(PLLA9FRACO_ENABLE_SHIFT);
+ writel_relaxed(con0, pll->con_reg);
+
+ /* Set PLL lock time. */
+ writel_relaxed(rate->pdiv * PLLA9FRACO_LOCK_FACTOR, pll->lock_reg);
+
+ /* Set PLL M, P, and S values. */
+ con0 &= ~((PLLA9FRACO_MDIV_MASK << PLLA9FRACO_MDIV_SHIFT) |
+ (PLLA9FRACO_PDIV_MASK << PLLA9FRACO_PDIV_SHIFT) |
+ (PLLA9FRACO_SDIV_MASK << PLLA9FRACO_SDIV_SHIFT));
+
+ /* The field FOUTPOSTDIVEN should always be 1, else FOUT might be 0 Hz. */
+ con0 |= (rate->mdiv << PLLA9FRACO_MDIV_SHIFT) |
+ (rate->pdiv << PLLA9FRACO_PDIV_SHIFT) |
+ (rate->sdiv << PLLA9FRACO_SDIV_SHIFT) | (PLLA9FRACO_FOUTPOSTDIVEN);
+
+ /* Set PLL K, DSM_EN and DAC_MODE values. */
+ con5 = readl_relaxed(pll->con_reg + PLLA9FRACO_PLL_CON5_DIV_FRAC);
+ con5 &= ~((PLLA9FRACO_KDIV_MASK << PLLA9FRACO_KDIV_SHIFT) |
+ PLLA9FRACO_DSM_EN | PLLA9FRACO_DAC_MODE);
+ con5 |= (rate->kdiv << PLLA9FRACO_KDIV_SHIFT) | PLLA9FRACO_DSM_EN | PLLA9FRACO_DAC_MODE;
+
+ /* Write configuration to PLL */
+ writel_relaxed(con0, pll->con_reg);
+ writel_relaxed(con5, pll->con_reg + PLLA9FRACO_PLL_CON5_DIV_FRAC);
+
+ /* Enable PLL */
+ con0 = readl_relaxed(pll->con_reg);
+ con0 |= BIT(PLLA9FRACO_ENABLE_SHIFT);
+ writel_relaxed(con0, pll->con_reg);
+
+ /* Wait for PLL lock if the PLL is enabled */
+ ret = samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
+ if (ret < 0)
+ return ret;
+
+ /* Select FOUT (1) */
+ con0 |= (PLLA9FRACO_MUX_SEL);
+ writel_relaxed(con0, pll->con_reg);
+
+ return 0;
+}
+
+static const struct clk_ops samsung_a9fraco_clk_ops = {
+ .recalc_rate = samsung_a9fraco_recalc_rate,
+ .determine_rate = samsung_pll_determine_rate,
+ .set_rate = samsung_a9fraco_set_rate,
+};
+
+static const struct clk_ops samsung_a9fraco_clk_min_ops = {
+ .recalc_rate = samsung_a9fraco_recalc_rate,
+};
+
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
const struct samsung_pll_clock *pll_clk)
{
@@ -1477,6 +1637,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
case pll_1452x:
case pll_142xx:
case pll_1017x:
+ case pll_a9fracm:
pll->enable_offs = PLL35XX_ENABLE_SHIFT;
pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
if (!pll->rate_table)
@@ -1578,6 +1739,14 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
else
init.ops = &samsung_pll1031x_clk_ops;
break;
+ case pll_a9fraco:
+ pll->enable_offs = PLLA9FRACO_ENABLE_SHIFT;
+ pll->lock_offs = PLLA9FRACO_LOCK_STAT_SHIFT;
+ if (!pll->rate_table)
+ init.ops = &samsung_a9fraco_clk_min_ops;
+ else
+ init.ops = &samsung_a9fraco_clk_ops;
+ break;
default:
pr_warn("%s: Unknown pll type for pll clk %s\n",
__func__, pll_clk->name);
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 6c8bb7f26da5..d6eb3246611b 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -51,6 +51,8 @@ enum samsung_pll_type {
pll_4311,
pll_1017x,
pll_1031x,
+ pll_a9fracm,
+ pll_a9fraco,
};
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
@@ -58,6 +60,11 @@ enum samsung_pll_type {
#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
+#define PLL_FRACO_RATE(_fin, _m, _p, _s, _k, _ks) \
+ ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) * ((_s) + 1)))
+#define PLL_FRACO_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
+ BUILD_BUG_ON_ZERO(PLL_FRACO_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
+
#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \
{ \
.rate = PLL_VALID_RATE(_fin, _rate, \
@@ -111,6 +118,16 @@ enum samsung_pll_type {
.vsel = (_vsel), \
}
+#define PLL_A9FRACO_RATE(_fin, _rate, _m, _p, _s, _k) \
+ { \
+ .rate = PLL_FRACO_VALID_RATE(_fin, _rate, \
+ _m, _p, _s, _k, 24), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
/* NOTE: Rate table should be kept sorted in descending order. */
struct samsung_pll_rate_table {
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 94b2bccc7d02..91e5cdbc79d7 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -359,8 +359,8 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
ctx->reg_base + list->offset, list->bit_idx,
list->gate_flags, &ctx->lock);
if (IS_ERR(clk_hw)) {
- pr_err("%s: failed to register clock %s: %ld\n", __func__,
- list->name, PTR_ERR(clk_hw));
+ pr_err("%s: failed to register clock %s: %pe\n", __func__,
+ list->name, clk_hw);
continue;
}
diff --git a/include/dt-bindings/clock/axis,artpec9-clk.h b/include/dt-bindings/clock/axis,artpec9-clk.h
new file mode 100644
index 000000000000..c6787be8d686
--- /dev/null
+++ b/include/dt-bindings/clock/axis,artpec9-clk.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2025 Axis Communications AB.
+ * https://www.axis.com
+ *
+ * Device Tree binding constants for ARTPEC-9 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_ARTPEC9_H
+#define _DT_BINDINGS_CLOCK_ARTPEC9_H
+
+/* CMU_CMU */
+#define CLK_FOUT_SHARED0_PLL 1
+#define CLK_DOUT_SHARED0_DIV2 2
+#define CLK_DOUT_SHARED0_DIV3 3
+#define CLK_DOUT_SHARED0_DIV4 4
+#define CLK_FOUT_SHARED1_PLL 5
+#define CLK_DOUT_SHARED1_DIV2 6
+#define CLK_DOUT_SHARED1_DIV3 7
+#define CLK_DOUT_SHARED1_DIV4 8
+#define CLK_FOUT_AUDIO_PLL 9
+#define CLK_DOUT_CMU_ADD 10
+#define CLK_DOUT_CMU_BUS 11
+#define CLK_DOUT_CMU_CDC_CORE 12
+#define CLK_DOUT_CMU_CORE_MAIN 13
+#define CLK_DOUT_CMU_CPUCL_SWITCH 14
+#define CLK_DOUT_CMU_DLP_CORE 15
+#define CLK_DOUT_CMU_FSYS0_BUS 16
+#define CLK_DOUT_CMU_FSYS0_IP 17
+#define CLK_DOUT_CMU_FSYS1_BUS 18
+#define CLK_DOUT_CMU_FSYS1_SCAN0 19
+#define CLK_DOUT_CMU_FSYS1_SCAN1 20
+#define CLK_DOUT_CMU_GPU_3D 21
+#define CLK_DOUT_CMU_GPU_2D 22
+#define CLK_DOUT_CMU_IMEM_ACLK 23
+#define CLK_DOUT_CMU_IMEM_CA5 24
+#define CLK_DOUT_CMU_IMEM_JPEG 25
+#define CLK_DOUT_CMU_IMEM_SSS 26
+#define CLK_DOUT_CMU_IPA_CORE 27
+#define CLK_DOUT_CMU_LCPU 28
+#define CLK_DOUT_CMU_MIF_SWITCH 29
+#define CLK_DOUT_CMU_MIF_BUSP 30
+#define CLK_DOUT_CMU_PERI_DISP 31
+#define CLK_DOUT_CMU_PERI_IP 32
+#define CLK_DOUT_CMU_RSP_CORE 33
+#define CLK_DOUT_CMU_TRFM 34
+#define CLK_DOUT_CMU_VIO_CORE_L 35
+#define CLK_DOUT_CMU_VIO_CORE 36
+#define CLK_DOUT_CMU_VIP0 37
+#define CLK_DOUT_CMU_VIP1 38
+#define CLK_DOUT_CMU_VPP_CORE 39
+#define CLK_DOUT_CMU_VIO_AUDIO 40
+
+/* CMU_BUS */
+#define CLK_MOUT_BUS_ACLK_USER 1
+
+/* CMU_CORE */
+#define CLK_MOUT_CORE_ACLK_USER 1
+
+/* CMU_CPUCL */
+#define CLK_FOUT_CPUCL_PLL0 1
+#define CLK_MOUT_CPUCL_PLL0 2
+#define CLK_FOUT_CPUCL_PLL1 3
+#define CLK_MOUT_CPUCL_PLL_SCU 4
+#define CLK_MOUT_CPUCL_SWITCH_SCU_USER 5
+#define CLK_MOUT_CPUCL_SWITCH_USER 6
+#define CLK_DOUT_CPUCL_CPU 7
+#define CLK_DOUT_CPUCL_CLUSTER_PERIPHCLK 8
+#define CLK_DOUT_CPUCL_CLUSTER_GICCLK 9
+#define CLK_DOUT_CPUCL_CLUSTER_PCLK 10
+#define CLK_DOUT_CPUCL_CMUREF 11
+#define CLK_DOUT_CPUCL_CLUSTER_ATCLK 12
+#define CLK_DOUT_CPUCL_CLUSTER_SCU 13
+#define CLK_DOUT_CPUCL_DBG 14
+#define CLK_GOUT_CPUCL_SHORTSTOP 15
+#define CLK_GOUT_CPUCL_CLUSTER_CPU 16
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK 17
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG 18
+
+/* CMU_FSYS0 */
+#define CLK_MOUT_FSYS0_BUS_USER 1
+#define CLK_MOUT_FSYS0_IP_USER 2
+#define CLK_MOUT_FSYS0_MAIN_USER 3
+#define CLK_DOUT_FSYS0_125 4
+#define CLK_DOUT_FSYS0_ADC 5
+#define CLK_DOUT_FSYS0_BUS_300 6
+#define CLK_DOUT_FSYS0_EQOS0 7
+#define CLK_DOUT_FSYS0_EQOS1 8
+#define CLK_DOUT_FSYS0_MMC_CARD0 9
+#define CLK_DOUT_FSYS0_MMC_CARD1 10
+#define CLK_DOUT_FSYS0_MMC_CARD2 11
+#define CLK_DOUT_FSYS0_QSPI 12
+#define CLK_DOUT_FSYS0_SFMC_NAND 13
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 14
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_CSR_I 15
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_PHASE_CLK_250 16
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_TXCLK 17
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_PHASE_CLK_250 18
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_TXCLK 19
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_ACLK_I 20
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_CLK_CSR_I 21
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_APB_S_PCLK 22
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_CORE_CLK 23
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_DMA_CLK 24
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_HDR_TX_CLK 25
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_APB_S_PCLK 26
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_CORE_CLK 27
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_DMA_CLK 28
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_HDR_TX_CLK 29
+#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_SDCLKIN 30
+#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_SDCLKIN 31
+#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_SDCLKIN 32
+#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_HCLK 33
+#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_SSI_CLK 34
+#define CLK_GOUT_FSYS0_SFMC_IPCLKPORT_I_ACLK_NAND 35
+#define CLK_GOUT_FSYS0_I2C0_IPCLKPORT_I_PCLK 36
+#define CLK_GOUT_FSYS0_I2C1_IPCLKPORT_I_PCLK 37
+#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_I_ACLK 38
+#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_I_ACLK 39
+#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_I_ACLK 40
+#define CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0 41
+
+/* CMU_FSYS1 */
+#define CLK_FOUT_FSYS1_PLL 1
+#define CLK_MOUT_FSYS1_SCAN0_USER 2
+#define CLK_MOUT_FSYS1_SCAN1_USER 3
+#define CLK_MOUT_FSYS1_BUS_USER 4
+#define CLK_DOUT_FSYS1_200 5
+#define CLK_DOUT_FSYS1_BUS_300 6
+#define CLK_DOUT_FSYS1_OTP_MEM 7
+#define CLK_DOUT_FSYS1_PCIE_PHY_REFCLK_SYSPLL 8
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_100 9
+#define CLK_GOUT_FSYS1_UART0_PCLK 10
+#define CLK_GOUT_FSYS1_UART0_SCLK_UART 11
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300 12
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC 13
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC 14
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC 15
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC 16
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC 17
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC 18
+#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 19
+#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 20
+#define CLK_GOUT_FSYS1_XHB_AHBBR_FSYS1_IPCLKPORT_CLK 21
+#define CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK 22
+
+/* CMU_IMEM */
+#define CLK_MOUT_IMEM_ACLK_USER 1
+#define CLK_MOUT_IMEM_CA5_USER 2
+#define CLK_MOUT_IMEM_SSS_USER 3
+#define CLK_MOUT_IMEM_JPEG_USER 4
+#define CLK_DOUT_IMEM_PCLK 5
+#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_ATCLK 6
+#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_CLKIN 7
+#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_PCLK_DBG 8
+#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_ATCLK 9
+#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_CLKIN 10
+#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_PCLK_DBG 11
+#define CLK_GOUT_IMEM_MCT0_PCLK 12
+#define CLK_GOUT_IMEM_MCT1_PCLK 13
+#define CLK_GOUT_IMEM_MCT2_PCLK 14
+#define CLK_GOUT_IMEM_MCT3_PCLK 15
+#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF 16
+
+/* CMU_PERI */
+#define CLK_MOUT_PERI_IP_USER 1
+#define CLK_MOUT_PERI_DISP_USER 2
+#define CLK_DOUT_PERI_125 3
+#define CLK_DOUT_PERI_PCLK 4
+#define CLK_DOUT_PERI_SPI 5
+#define CLK_DOUT_PERI_UART1 6
+#define CLK_DOUT_PERI_UART2 7
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK 8
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK 9
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_APB_S_PCLK 10
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_CORE_CLK 11
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_DMA_CLK 12
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_HDR_TX_CLK 13
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_APB_S_PCLK 14
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_CORE_CLK 15
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_DMA_CLK 16
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_HDR_TX_CLK 17
+#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 18
+#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK 19
+#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK 20
+#define CLK_GOUT_PERI_SPI0_PCLK 21
+#define CLK_GOUT_PERI_SPI0_SCLK_SPI 22
+#define CLK_GOUT_PERI_UART1_PCLK 23
+#define CLK_GOUT_PERI_UART1_SCLK_UART 24
+#define CLK_GOUT_PERI_UART2_PCLK 25
+#define CLK_GOUT_PERI_UART2_SCLK_UART 26
+
+#endif /* _DT_BINDINGS_CLOCK_ARTPEC9_H */
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index 80dacda57229..95285589615a 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -126,6 +126,7 @@
#define CLK_GOUT_GPIO_ALIVE_PCLK 22
#define CLK_GOUT_PMU_ALIVE_PCLK 23
#define CLK_GOUT_SYSREG_APM_PCLK 24
+#define CLK_GOUT_MAILBOX_APM_AP_PCLK 25
/* CMU_AUD */
#define CLK_DOUT_AUD_AUDIF 1
diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h
index 06dec27a8c77..f2628c220b22 100644
--- a/include/dt-bindings/clock/samsung,exynosautov920.h
+++ b/include/dt-bindings/clock/samsung,exynosautov920.h
@@ -309,4 +309,10 @@
#define CLK_MOUT_MFD_NOC_USER 1
#define CLK_DOUT_MFD_NOCP 2
+/* CMU_G3D */
+#define FOUT_PLL_G3D 1
+#define CLK_MOUT_G3D_NOC 2
+#define CLK_MOUT_G3D_SWITCH_USER 3
+#define CLK_MOUT_G3D_NOCP_USER 4
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-13 11:25:16 +0300