diff options
| author | Amit Cohen <amcohen@nvidia.com> | 2023-01-19 13:32:27 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2023-01-21 05:50:15 +0300 |
| commit | 42b4f757ba9c4990dc3c26f0d54a3259ad761613 (patch) | |
| tree | 601a824a6ee25176936a3ced8522de36ff1059f0 | |
| parent | 24a7fffb2533bb44d4ec84bb824732a9c4882f15 (diff) | |
| download | linux-42b4f757ba9c4990dc3c26f0d54a3259ad761613.tar.xz | |
mlxsw: reg: Add TLV related fields to MGIR register
MGIR (Management General Information Register) allows software to query the
hardware and firmware general information. As part of firmware information,
the driver can query if string TLV and latency TLV are supported. These
TLVs are part of EMAD's header and are used to provide information per
EMAD packet to software.
Currently, string TLV is already used by the driver, but it does not
query if this TLV is supported from MGIR. The next patches will add support
of latency TLV. Add the relevant fields to MGIR, so then the driver will
query them to know if the TLVs are supported before using them.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/reg.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index f2d6f8654e04..8165bf31a99a 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -10009,6 +10009,18 @@ MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); */ MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); +/* reg_mgir_fw_info_latency_tlv + * When set, latency-TLV is supported. + * Access: RO + */ +MLXSW_ITEM32(reg, mgir, fw_info_latency_tlv, 0x20, 29, 1); + +/* reg_mgir_fw_info_string_tlv + * When set, string-TLV is supported. + * Access: RO + */ +MLXSW_ITEM32(reg, mgir, fw_info_string_tlv, 0x20, 28, 1); + #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 /* reg_mgir_fw_info_psid |