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authorShuijing Li <shuijing.li@mediatek.com>2024-04-12 06:11:39 +0300
committerChun-Kuang Hu <chunkuang.hu@kernel.org>2024-04-22 16:40:34 +0300
commit417d8c47271d5cf1a705e997065873b2a9a36fd4 (patch)
tree39884383246c70de18d87f2ab849d9764e73a95e
parent8431fff9e0f3fc1c5844cf99a73b49b63ceed481 (diff)
downloadlinux-417d8c47271d5cf1a705e997065873b2a9a36fd4.tar.xz
drm/mediatek: dsi: Correct calculation formula of PHY Timing
This patch correct calculation formula of PHY timing. The spec define HS-PREPARE should be from 40ns+4*UI(44ns) to 85ns+6*UI(91ns). But current duration is 88ns and is near the boundary. So this patch make the duration to 64ns so it is near the safe range. Signed-off-by: Shuijing Li <shuijing.li@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20240412031208.30688-1-shuijing.li@mediatek.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
-rw-r--r--drivers/gpu/drm/mediatek/mtk_dsi.c31
1 files changed, 16 insertions, 15 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 67239606adbf..c255559cc56e 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -242,22 +242,23 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ);
struct mtk_phy_timing *timing = &dsi->phy_timing;
- timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
- timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
- timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
+ timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1;
+ timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / 8000 + 1;
+ timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / 8000 + 1 -
timing->da_hs_prepare;
- timing->da_hs_trail = timing->da_hs_prepare + 1;
-
- timing->ta_go = 4 * timing->lpx - 2;
- timing->ta_sure = timing->lpx + 2;
- timing->ta_get = 4 * timing->lpx;
- timing->da_hs_exit = 2 * timing->lpx + 1;
-
- timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
- timing->clk_hs_post = timing->clk_hs_prepare + 8;
- timing->clk_hs_trail = timing->clk_hs_prepare;
- timing->clk_hs_zero = timing->clk_hs_trail * 4;
- timing->clk_hs_exit = 2 * timing->clk_hs_trail;
+ timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1;
+
+ timing->ta_go = 4 * timing->lpx;
+ timing->ta_sure = 3 * timing->lpx / 2;
+ timing->ta_get = 5 * timing->lpx;
+ timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;
+
+ timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) + 1;
+ timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) / 8000 + 1;
+ timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1;
+ timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1 -
+ timing->clk_hs_prepare;
+ timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;
timcon0 = FIELD_PREP(LPX, timing->lpx) |
FIELD_PREP(HS_PREP, timing->da_hs_prepare) |