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| author | Huacai Chen <chenhuacai@loongson.cn> | 2025-03-30 11:31:09 +0300 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2025-03-30 11:31:09 +0300 |
| commit | 4103cfe9dcb88010ae4911d3ff417457d1b6a720 (patch) | |
| tree | 81a36e3e46208133e76d3d83c000d27d6314094d | |
| parent | ec105cadff5d8c0a029a3dc1084cae46cf3f799d (diff) | |
| download | linux-4103cfe9dcb88010ae4911d3ff417457d1b6a720.tar.xz | |
LoongArch: Increase ARCH_DMA_MINALIGN up to 16
ARCH_DMA_MINALIGN is 1 by default, but some LoongArch-specific devices
(such as APBDMA) require 16 bytes alignment. When the data buffer length
is too small, the hardware may make an error writing cacheline. Thus, it
is dangerous to allocate a small memory buffer for DMA. It's always safe
to define ARCH_DMA_MINALIGN as L1_CACHE_BYTES but unnecessary (kmalloc()
need small memory objects). Therefore, just increase it to 16.
Cc: stable@vger.kernel.org
Tested-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
| -rw-r--r-- | arch/loongarch/include/asm/cache.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/loongarch/include/asm/cache.h b/arch/loongarch/include/asm/cache.h index 1b6d09617199..aa622c754414 100644 --- a/arch/loongarch/include/asm/cache.h +++ b/arch/loongarch/include/asm/cache.h @@ -8,6 +8,8 @@ #define L1_CACHE_SHIFT CONFIG_L1_CACHE_SHIFT #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define ARCH_DMA_MINALIGN (16) + #define __read_mostly __section(".data..read_mostly") #endif /* _ASM_CACHE_H */ |