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| author | Mark Brown <broonie@kernel.org> | 2025-07-23 15:27:45 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2025-09-08 15:25:38 +0300 |
| commit | 3c0979c64481f07a6bf9c1775601845ac5fa57f3 (patch) | |
| tree | caf89b57dbbf48cbacd350d9f6857171ad378c7f | |
| parent | 8f5ae30d69d7543eee0d70083daf4de8fe15d585 (diff) | |
| download | linux-3c0979c64481f07a6bf9c1775601845ac5fa57f3.tar.xz | |
arm64/sme: Drop inaccurate documentation of streaming mode switches
The SME ABI documentation contains an inaccurate description of the
architectural streaming mode entry/exit behaviour, just remove it since
this is better documented by the architecture or with the rest of the
documentation for the specific software interfaces concerned.
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | Documentation/arch/arm64/sme.rst | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/Documentation/arch/arm64/sme.rst b/Documentation/arch/arm64/sme.rst index 4cb38330e704..583f2ee9cb97 100644 --- a/Documentation/arch/arm64/sme.rst +++ b/Documentation/arch/arm64/sme.rst @@ -81,17 +81,7 @@ The ZA matrix is square with each side having as many bytes as a streaming mode SVE vector. -3. Sharing of streaming and non-streaming mode SVE state ---------------------------------------------------------- - -It is implementation defined which if any parts of the SVE state are shared -between streaming and non-streaming modes. When switching between modes -via software interfaces such as ptrace if no register content is provided as -part of switching no state will be assumed to be shared and everything will -be zeroed. - - -4. System call behaviour +3. System call behaviour ------------------------- * On syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the @@ -112,7 +102,7 @@ be zeroed. exceptions for execve() described in section 6. -5. Signal handling +4. Signal handling ------------------- * Signal handlers are invoked with PSTATE.SM=0, PSTATE.ZA=0, and TPIDR2_EL0=0. |