diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2026-03-12 19:04:07 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-03-20 13:23:18 +0300 |
| commit | 3a7e37edaa071faba1a69d400f091b14eb8bc21f (patch) | |
| tree | 80eb90ec4eca0e2130a71f542ca90ff7d2571d9f | |
| parent | 4926ff5231f4d5f7e0084e3a5c0bc7d2e34aecde (diff) | |
| download | linux-3a7e37edaa071faba1a69d400f091b14eb8bc21f.tar.xz | |
arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add PHY interrupt support
Add interrupt support for the GMAC1 and GMAC2 PHYs on the RZ/T2H EVK
board. The PHYs are connected to the ICU via IRQ3 and IRQ13 lines
respectively.
Define RZT2H_IRQxx macros in the SoC DTSI to map the ICU IRQ_NS lines
to their absolute ICU interrupt space offsets.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260312160407.3387840-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 18 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts | 8 |
2 files changed, 24 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 81f6a36e6e72..3761551c9647 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -8,6 +8,24 @@ #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +/* The IRQ_NS lines start at offset 16 in the ICU interrupt space */ +#define RZT2H_IRQ0 16 +#define RZT2H_IRQ1 17 +#define RZT2H_IRQ2 18 +#define RZT2H_IRQ3 19 +#define RZT2H_IRQ4 20 +#define RZT2H_IRQ5 21 +#define RZT2H_IRQ6 22 +#define RZT2H_IRQ7 23 +#define RZT2H_IRQ8 24 +#define RZT2H_IRQ9 25 +#define RZT2H_IRQ10 26 +#define RZT2H_IRQ11 27 +#define RZT2H_IRQ12 28 +#define RZT2H_IRQ13 29 +#define RZT2H_IRQ14 30 +#define RZT2H_IRQ15 31 + / { compatible = "renesas,r9a09g077"; #address-cells = <2>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 49464e6d212b..52e5f6c3ab67 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -227,10 +227,12 @@ }; &mdio1_phy { + interrupts-extended = <&icu RZT2H_IRQ3 IRQ_TYPE_EDGE_FALLING>; reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>; }; &mdio2_phy { + interrupts-extended = <&icu RZT2H_IRQ13 IRQ_TYPE_EDGE_FALLING>; /* * PHY2 Reset Configuration: * @@ -277,7 +279,8 @@ <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */ <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */ <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */ - <RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */ + <RZT2H_PORT_PINMUX(31, 0, 0x2)>, /* ETH2_REFCLK */ + <RZT2H_PORT_PINMUX(31, 1, 0x0)>; /* IRQ13 */ }; /* @@ -305,7 +308,8 @@ <RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */ <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */ <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */ - <RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */ + <RZT2H_PORT_PINMUX(34, 6, 0x2)>, /* ETH3_REFCLK */ + <RZT2H_PORT_PINMUX(27, 2, 0x0)>; /* IRQ3 */ }; /* |